We research cyber security and teach future’s experts
to ensure secure technology in everyone’s life.
Trust, Security and Identify Managament: The Austrian Viewpoint
Posch R.
Conference on Trust and Identity Management
Eine 8-bit Highspeed Softwareimplementierung von Whirlpool
Könighofer R., Berger S., Herbst C.
DACH Security 2007
Energy Evaluation of Software Implementations of Block Ciphers under Memory Constraints
Großschädl J., Tillich S., Rechberger C., Hofmann M., Medwed M.
Proceedings of the 10th Conference on Design, Automation and Test in Europe (DATE 2007)
Implementation Aspects of the DPA-Resistant Logic Style MDPL
Popp T., Mangard S.
IEEE International Symposium on Circuits and Systems
Practical Second-Order DPA Attacks for Masked Smart Card Implementations of Block Ciphers
Oswald M., Mangard S., Herbst C., Tillich S.
Topics in Cryptology - CT-RSA 2006
An AES Smart Card Implementation resitant to Power Analysis Attacks
Herbst C., Oswald M., Mangard S.
Applied cryptography and Network security
Pinpointing the Side-Channel Leakage of Masked CMOS Implementations
Mangard S., Schramm K.
Cryptographic Hardware and Embedded Systems - CHES 2006
Side Channel Analysis Resistant Design Flow
Aigner M., Popp T., Mangard S., Trifiletti A., Menicocci R., Olivieri M., Scotti G.
IEEE International Symposium on Circuits and Systems
Compositional SCC analysis for language emptiness
Wang C., Bloem R., Hachtel G., Ravi K., Somenzi F.
Formal Methods in System Design, Vol. 28(1), 2006
Symbolic implementation of alternating automata
Pill I., Bloem R., Cimatti A., Roveri M., Semprini S.
Implementation and application of automata
Formal analysis of hardware requirements
Pill I., Bloem R., Semprini S., Roveri M., Cimatti A., Cavada R.
Design Automation Conference
Repair of boolean programs with an application to C
Griesmayer A., Bloem R., Byron C.
Computer Aided Verification
Automated Fault Localization for C Programs
Griesmayer A., Staber S., Bloem R.
Workshop on Verification and Debugging
Game-based and simulation-based improvements for LTL synthesis
Jobstmann B., Bloem R.
Games in Design and Verification
Rat: A tool for formal analysis of requirements
Pill I., Bloem R., Cimatti A., Roveri M., Semprini S., Tchaltsev A.
European Conference on Artificial Intelligence
Automatic Fault Localization for Property Checking
Staber S., Fey G., Bloem R., Drechsler R.
Haifa Verification Conference
Optimizations for LTL synthesis
Jobstmann B., Bloem R.
International Conference on Formal Methods in Computer-Aided Design
Identification in E-Government: An Overview of Approaches
Leitold H., Posch R.
Encyclopedia of Digital Government, IDEA Group, 984-987, 2006
Communications and Multimedia Security
Leitold H., Markatos E.
Springer Berlin / Heidelberg, 2006