We research cyber security and teach future’s experts
to ensure secure technology in everyone’s life.
Collisions and other Non-Random Properties for Step-Reduced SHA-256
Indesteege S., Mendel F., Preneel B., Rechberger C.
Selected Areas in Cryptography
Preimages for Reduced SHA-0 and SHA-1
De Cannière C., Rechberger C.
Advances in Cryptology - Proceedings CRYPTO 2008
Cryptanalysis of the GOST Hash Function
Mendel F., Pramstaller N., Rechberger C., Kontak M., Szmidt J.
Advances in Cryptology - Proceedings CRYPTO 2008
Boosting AES Performance on a Tiny Processor Core
Tillich S., Herbst C.
Topics in Cryptology - CT-RSA 2008
Attacking State-of-the-Art Software Countermeasures—A Case Study for AES
Tillich S., Herbst C.
Cryptographic Hardware and Embedded Systems - CHES 2008
Enhancing Side-Channel Analysis with Low-Cost Shielding Techniques
Plos T., Hutter M., Herbst C.
Tagungsband, Austrochip 2008, Linz, Austria, October 8, 2008, Proceedings
Power Analysis Attacks - Revealing the Secrets of Smart Cards
Mangard S., Oswald M., Popp T.
Springer, 2007
Power Analysis Attacks and Countermeasures
Popp T., Mangard S., Oswald M.
IEEE design & test of computers, Vol. 24(6), 2007
Power and EM Attacks on Passive 13.56 MHz RFID Devices
Hutter M., Mangard S., Feldhofer M.
Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings
Protecting AES Software Implementations on 32-bit Processors against Power Analysis
Tillich S., Herbst C., Mangard S.
Applied Cryptography and Network Security
Template Attacks on Masking - Resistance Is Futile
Oswald E., Mangard S.
Cryptographers´ Track at the RSA Conference
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
Popp T., Kirschbaum M., Zefferer T., Mangard S.
Cryptographic Hardware and Embedded Systems - CHES 2007
Symbolic Implementation of Alternating Automata
Bloem R., Cimatti A., Pill I., Roveri M.
International journal of foundations of computer science, Vol. 18(4), 2007
Specify, Compile, Run: Hardware from PSL
Bloem R., Galler S., Jobstmann B., Piterman N., Pnueli A., Weiglhofer M.
6th International Workshop on Compiler Optimization Meets Compiler Verification
Anzu: A Tool for Property Synthesis
Jobstmann B., Galler S., Weiglhofer M., Bloem R.
Proceedings of the 19th International Conference of Computer Aided Verification 2007
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Bloem R., Galler S., Jobstmann B., Piterman N., Pnueli A., Weiglhofer M.
Proceedings of the conference on Design, automation and test in Europe
RAT: A Tool for the Formal Analysis of Requirements
Bloem R., Cavada R., Pill I., Roveri M., Tchaltsev A.
19th International Conference, CAV 2007, Berlin, Germany, July 3-7, 2007. Proceedings
Fault localization and correction with QBF
Staber S., Bloem R.
Theory and Applications of Satisfiability Testing – SAT 2007
Attacking DPA-Resistant Logic Styles in Practice
Zefferer T.
Master's Thesis, 2007