Publications and Talks

Accelerating Isogeny Walks for VDF Evaluation

Jacquemin D., Mukherjee A., Mert A., Sinha Roy S.
IACR Communications in Crypology, Vol. 2(1)

REED

Aikata A., Mert A., Kwon S., Deryabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(2), 163-208

Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing

Krieger F., Hirner F., Sinha Roy S.
DATE 2025, 2025 Design, Automation and Test in Europe Conference: DATE 2025, 1-7

PASTA on Edge: Cryptoprocessor for Hybrid Homomorphic Encryption

Aikata A., Sanz Sobrino D., Sinha Roy S.
DATE: Design, Automation and Test in Europe Conference, 2025 Design, Automation and Test in Europe Conference: DATE 2025

REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption

Aikata A., Mert A., Kwon S., Deryabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(2)

Simple Power Analysis Attack on SQIsign

Mukherjee A., Czuprynko M., Jacquemin D., Kutas P., Sinha Roy S.
Africacrypt 2025, 16th International Conference on Cryptology, Progress in Cryptology - AFRICACRYPT 2025

Correlation power analysis of LESS and CROSS

Czuprynko M., Mukherjee A., Sinha Roy S.
Africacrypt 2025, 16th International Conference on Cryptology, Progress in Cryptology - AFRICACRYPT 2025

Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms

Hirner F., Streibl M., Krieger F., Mert A., Sinha Roy S.
CCS 2024 - Proceedings of the 2024 ACM SIGSAC Conference on Computer and Communications Security, ACM Conference on Computer and Communications Security, CCS 2024, 3421-3435

Proteus: A Pipelined NTT Architecture Generator

Hirner F., Mert A., Sinha Roy S.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 32(7), 1228 - 1238

Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs

Ravi P., Bhasin S., Chattopadhyay A., Aikata A., Sinha Roy S.
GLSVLSI 2024 - Proceedings of the Great Lakes Symposium on VLSI 2024, 34th Great Lakes Symposium on VLSI, 216 - 221

Aloha-HE: A Low-Area Hardware Accelerator for Client-Side Operations in Homomorphic Encryption

Krieger F., Hirner F., Mert A., Sinha Roy S.
DATE 2024, 2024 Design, Automation and Test in Europe Conference, 1-6

OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE

Krieger F., Hirner F., Mert A., Sinha Roy S.
ICCAD 2024, ACM/IEEE, 1-9

ModHE: Modular Homomorphic Encryption Using Module Lattices

Mukherjee A., Aikata A., Mert A., Lee Y., Kwon S., Deriyabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2024(1), 527-562

REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography

Pagliarini S., Aikata A., Imran M., Sinha Roy S.
AsiaCCS

Exploring the Advantages and Challenges of Fermat NTT in FHE Acceleration

Kim A., Mert A., Mukherjee A., Aikata A., Deryabin M., Kwon S., Kang H., Sinha Roy S.
Advances in Cryptology – CRYPTO 2024 - 44th Annual International Cryptology Conference, Proceedings, 44th Annual International Cryptology Conference, 76–106, (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); vol. 14922 LNCS)

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