A modular interpretation of the Hessian of elliptic curves

Abstract

In this talk, we will discuss the modular interpretation of the Hessian transformation on elliptic curves. We begin by recalling some classical results concerning the action of the Hessian transforma-tion on the j-invariants and on the Hesse pencil, and we rephrase them in the context of the modu-lar curves X(1) and X(3). Building on the work of Mula, Pintore, and Taufer in the recent preprint (ArXiv:2407.17042), we lift the Hessian transformation up to maps on 16 different modular curves, in-cluding X(6), and analyse their effects on the associated moduli spaces. Finally, we give a numerical representation of Hessian map on the extended complex upper half-plane H∗. This talk is based on the speaker’s Master’s thesis supervised by Pintore, Taufer and Mula.



Bio

Riccardo Lolato — Master’s degree in Mathematics – Cryptography, Universita` degli Studi di Trento.



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25th International Conference on Runtime Verification

From September 15 to 19, 2025, we’re hosting the 25th International Conference on Runtime Verification (RV 2025) at TU Graz!

The RV series is an annual event that brings together researchers and practitioners from academia and industry who are interested in novel, lightweight formal methods for monitoring, analyzing, and guiding the runtime behavior of software and hardware systems. Runtime verification techniques play a vital role in ensuring system correctness, reliability, and robustness. They offer an additional layer of rigor and effectiveness compared to conventional testing, while remaining more practical than exhaustive formal verification.

This year’s edition features three co-located workshops – RVmeetsMBD, RVCase, and VASSAL – which will take place on September 15. We are also delighted to welcome an outstanding lineup of keynote speakers: Thomas Henzinger, Nils Jansen, Ankush Desai, and Daniela Micucci.

Memory-Centric Computing: Enabling Fundamentally Efficient & Intelligent Machines

Abstract
Computing is bottlenecked by data. Large amounts of application data overwhelm the storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern computers in terms of 1) dealing with data, 2) taking advantage of vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent computing architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give examples of how to exploit these principles to design a much more efficient and higher performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits the fundamental operational properties of memory chips to perform massively-parallel computation in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory chips, the logic layer of 3D-stacked technologies, or memory controllers to enable near-memory computation with high memory bandwidth and low memory latency. We show both types of architectures can enable order(s) of magnitude improvements in performance and energy consumption of many important workloads, such as artificial intelligence, machine learning, graph analytics, database systems, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs.

An accompanying overview of modern memory-centric computing ideas & systems can be found at arxiv.org/pdf/2012.03112 (“A Modern Primer on Processing in Memory”, updated February 2025).

A shorter invited paper from IMW 2025 is at arxiv.org/pdf/2505.00458 (“Memory-Centric Computing: Solving Computing’s Memory Problem”, May 2025)



Bio

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His current research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. Many techniques he, with his group and collaborators, has invented over the years have largely influenced industry and have been widely employed in commercial microprocessors and memory & storage systems used daily by hundreds of millions of people. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems,” 2024 IFIP WG10.4 Jean-Claude Laprie Award in Dependable Computing (for the original RowHammer work), 2022 Persistent Impact Prize of the Non-Volatile Memory Systems Workshop (for original architectural work on Phase Change Memory), 2021 IEEE High Performance Computer Architecture Conference Test of Time Award (for the Runahead Execution work), 2020 IEEE Computer Society Edward J. McCluskey Technical Achievement Award, 2019 ACM SIGARCH Maurice Wilkes Award and more than thirty best paper, “Top Pick” paper, or test-of-time recognitions at various leading computer systems, architecture, and security venues. He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 24 PhD graduates, many of whom received major dissertation awards, 15 postdoctoral trainees, and more than 60 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube (OnurMutluLectures@CMUCompArch), and his research group makes a wide variety of open-source artifacts freely available online. For more information, please see his webpage.



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Green Intelligent & Connected Systems with Sensory Intelligence on Chip: Pushing AI Out of the Cloud and into the Physical World

Abstract 

Recent semiconductor scaling trends continue to support the evolution of intelligent and connected silicon systems. Such evolution vastly outranges any application ever deployed by human beings, and its sustained growth is now fundamentally impeded by the ludicrously high levels of power consumption that next-generation datacenters are expected to require. At the same time, moving intelligence into trillion-scale distributed edge devices is fundamentally impeded by batteries, which threaten economic and environmental sustainability of the underlying scaling trend, and hence feasibility.

This talk introduces key ideas and silicon demonstrations to enable a new breed of always-on silicon systems with sensory intelligence with no battery inside (or any other energy storage). Highly power-scalable systems with adaptation to the highly-fluctuating power profile of energy harvesters is shown to enable next-generation pervasive integrated systems with cost well below 1$, size of few millimeters, long lifetime well beyond the traditional shelf life of batteries, yet at near-100% up-time.

Sensor interfaces, processors and wireless transceivers fitting existing infrastructure (e.g., WiFi, Bluetooth) with power reductions by orders of magnitude and down to sub-leakage are exemplified by numerous silicon demonstrations from our Green IC research group, along with their system integration. Ultimately, the technological pathway discussed in this talk supports sustainable growth of applications leveraging large-scale deployments of silicon systems, making our planet smarter. And greener too.



Bio

Massimo Alioto is Provost’s Chair Professor at the ECE Department of the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan – Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL – Lausanne.

He is (co)author of 400 publications on journals and conference proceedings, and four books with Springer (with two more coming). His primary research interests include ultra-low power and self-powered systems, green computing, circuits for machine intelligence, hardware security, and emerging technologies.

He was the Editor in Chief of the IEEE Transactions on VLSI Systems and Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. He was the Chair of the Distinguished Lecturer Program for the IEEE CAS Society, and was a Distinguished Lecturer for the SSC and CAS Society. Previously, Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE Circuits and Systems Society (2010-2012). He served as Guest Editor of numerous journal special issues (JSSC, TCAS-I, JETCAS…), Technical Program Chair of several IEEE conferences (ISCAS, SOCC, PRIME, ICECS), and TPC member (ISSCC, ASSCC). His research group contribution has been recognized through various best paper awards (e.g., ISSCC), and in the ten technological highlights of the TSMC annual report, among the others. Prof. Alioto is an IEEE Fellow.




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Tweakable enciphering modes and their Committing Security

Abstract
A tweakable enciphering mode (TEM) is a cryptographic primitive that provides length-preserving encryption. In 2024, the National Institute of Standards and Technology (NIST) issued the Accordion call to standardize future-proof TEMs. TEMs serve as building blocks for various modes of operation, including authenticated encryption (AE), deterministic AE (DAE) and disk encryption. NIST has identified context commitment (CMT-4) as an important security objective for TEMs when used in AE/DAE.

We will start the talk by discussing the challenges of CMT-4 secure TEMs. In particular, we show that many existing TEMs, such as HCTR2 and Adiantum, fail to achieve CMT-4. We discuss different approaches to remedy the situation, and conclude our talk by proposing novel TEM designs, which are the first to achieve provably CMT-4 security.

Polycrypt: Beyond the Linicrypt model

Abstract
The Linicrypt framework (Carmer and Rosulek, Crypto’16) provides a foundation for systematic, automated reasoning about cryptographic programs whose primitive instructions include randomly sampling, evaluating linear combinations, and querying a random oracle over some known finite field. Later, McQuoid et al. (TCC’19) gave a characterization of collision and second-preimage resistance for a class of programs, for which such properties can be checked in polynomial time. Other works have then extended similar characterizations to alternative notions either in the pseudo-random permutation (PRP) or in the ideal cipher (IC) model. None of these variations provides a way to reason about programs which employ non-linear operations over their state.

In this talk we will introduce the Polycrypt framework, an extension of Linicrypt which admits the evaluation of arbitrary polynomial transformations over the underlying field. We show how to algebraically represent such programs, and in particular we demonstrate how it naturally allows us to model important security properties such as collision and second preimage resistance. We characterize a class of “sparse” programs which admits a polynomial-time algorithm to establish collision/second-preimage resistance. We also show that Polycrypt can be readily extended to the IC model, where it can be employed to automatically verify security properties of constructions that intrinsically make use of non-linear components, such as the Galois Counter Mode (GCM) and extensions thereof.

CS-Talk #16: Can big data solve safety and security problems?

Abstract
Critical industries like avionics or automotive have the possibility of collecting large sets of data during the functioning of their products. Originally dedicated to vital functions as safety and security, data may be collected to any component level nowadays. This is due to the replacement of analogical and mechanical parts by electrical solutions. For instance, an automotive braking system may be replaced, completely, by a X by Wire solution, meaning that the hydraulic components are replaced by electrical components. To keep safeness and security as accurate as previous components, the sampling frequency of electrical components (sensors, engines, etc) is as high as possible, producing large sets of data. Under the pressure of other industries that benefit from the arrival of statistical methods and models dealing with large sets of data to accelerate their development cycles, critical industries analyze the possibility to integrate such methods and models within their own development cycle. Within this talk, we present pros and cons on the utilization of existing large sets of data, while focusing on the safety.



Bio
Liliana Cucu-Grosjean is a Research Director at the French National Institute in Computer Science and Automation (Inria) in Paris, France, where she leads the Kopernic research team. Her research interests include real-time, embedded and cyber-physical systems with a focus on the use of probabilistic and statistical methods for analyzing the schedulability of programs and estimating worst-case execution of those programs. Co-author of several seminal papers on probabilistic and statistical methods for real-time systems, Liliana has published more than 60 papers in top TCRTS conferences and journals. Chair of the first TCRTS diversity sub-committees (2016 to 2020), she has also co-founded the Inria diversity committee in 2015, that she co-chaired until 2022. Since January 2023, she has been the elected IEEE TCRTS vice-chair. Since December 2019, she has been co-founder of the start-up StatInf, an Inria spin-off.


Organizer: Dean’s Office CSBME
More: CS Talk #16
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Towards a Secure and Privacy-Respecting Web

Abstract  
The Hypertext Transfer Protocol, generally displayed as http in a browsers address-bar, is the fundamental protocol through which web browsers and websites communicate. However, data transferred by the regular http protocol is unprotected and transferred in cleartext, such that attackers are able to view, steal, or even tamper with the transmitted data. Carrying http over the Transport Layer Security (TLS) protocol, generally displayed as https in the address-bar of a browser, fixes this security shortcoming by creating a secure and encrypted connection between the browser and the website.
Over the past few years we have witnessed tremendous progress towards migrating the web to rely on https instead of the outdated and insecure http protocol. Within this talk we will highlight initiatives from browser vendors as well as community efforts to accelerate the migration from http to https and explore additional privacy mechanisms within a web browser which eventually will provide a browsing experience we want: secure and privacy-respecting!



Bio
Dr. Christoph Kerschbaumer has over two decades of experience in software engineering and computer security. His work ranges from designing secure systems with fail-safe defaults to fighting cross-site scripting to preventing machine-in-the-middle attacks. Currently he is managing the Firefox Security Engineering team at Mozilla and is mentoring software engineers around the world to reach their full potential. He received his PhD in Computer Science from the University of California, Irvine, where he focused his research on information flow tracking techniques within web browsers. Prior to being a graduate research scholar, he received a M.Sc. and B.Sc. in Computer Science from the Technical University Graz, Austria.



More: christophkerschbaumer.com
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Security of the Ascon Modes

Abstract 

The Ascon authenticated encryption scheme and hash function of Dobraunig et al. (Journal of Cryptology 2021) were recently selected as winner of the NIST lightweight cryptography competition. The mode underlying Ascon authenticated encryption (Ascon-AE) resembles ideas of SpongeWrap, but not quite, and various works have investigated the generic security of Ascon-AE, all covering different attack scenarios and with different bounds.

This work systematizes knowledge on the mode security of Ascon-AE, and fills gaps where needed. We consider six mainstream security models, all in the multi-user setting: (i) nonce-respecting security, reflecting on the existing bounds of Chakraborty et al. (ASIACRYPT 2023, ACISP 2024) and Lefevre and Mennink (SAC 2024), (ii) nonce-misuse resistance, observing a non-fixable flaw in the proof of Chakraborty et al. (ACISP 2024), (iii) nonce-misuse resilience, delivering missing security analysis, (iv) leakage resilience, delivering a new security analysis that supersedes the informal proof sketch (though in a different model) of Guo et al. (ToSC 2020), (v) state-recovery security, expanding on the analysis of Lefevre and Mennink, and (vi) release of unverified plaintext, also delivering missing security analysis. We also match all bounds with tight attacks (up to constant and up to reasonable assumptions). As a bonus, we systematize the knowledge on Ascon-Hash and Ascon-PRF.



Bio
Bart Mennink received his PhD in May 2013 from KU Leuven, Belgium, and has subsequently been a postdoctoral researcher at KU Leuven and in the Digital Security group at Radboud University Nijmegen. Currently, he is associate professor on cryptography in the Digital Security Group at Radboud University Nijmegen. His main field of research is the design and provable security of symmetric cryptographic protocols, with the current focus on lightweight authentication and encryption. Bart Mennink is co-designer of Chaskey, and ISO standardized MAC function, and of COLM, an authenticated encryption scheme that was selected for the final portfolio of the CAESAR competition. He is furthermore co-designer of Elephant and ISAP, finalist authenticated encryption schemes in the NIST Lightweight Cryptography competition. Bart has published over 100 articles, he has been (co-)organizer of multiple international conferences and workshops, and has given over 15 keynotes at various conferences and workshops.



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Weird Microarchitectural Gates – Beyond Boolean Logic

Abstract 

Over the last few years, multiple works have investigated the ability for performing computation on microarchitectural state. These works demonstrate techniques for creating weird gates that use microarchitectural state to represent Boolean values and perform logical functions on this state. Beyond showing that the gates are functionally complete, i.e., that they can compute any Boolean function, these works explore the security implications of using these gates.

This talk observes that the semantics of both microarchitectural state and weird gates extend well beyond Boolean logic and allow a much richer set of operations. We show how these semantics can be used for interrogating the hardware at a high precision and to improve the temporal resolution of cache attacks.



Bio


Yuval Yarom is a Professor of Computer Security at Ruhr University Bochum. His research focuses on the interface between the software and the hardware. In particular, He is interested in the discrepancy between the way that programmers think about software execution and the concrete execution in modern processors. He is a recipient of a 2020 ARC Discovery Early Career Award and the 2020 CORE Chris Wallace Award for Outstanding Research, a 2020 Young Tall Poppy. His research has won best paper awards at CCS 2024, PLDI 2023, IEEE SP 2019, EuroSys 2019, ApSys 2018, and best student paper award at ICEIS 2020. Previously, he has been an Associate Professor at the University of Adelaide, the Vice President of Research in Memco Software, and a co-founder and Chief Technology Officer of Girafa.com. Yuval earned his Ph.D. in Computer Science from the University of Adelaide in 2014, and an M.Sc. in Computer Science and a B.Sc. in Mathematics and Computer Science from the Hebrew University of Jerusalem in 1993 and 1990, respectively.



More: https://yuval.yarom.org
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