Abstract

The first Rowhammer exploit was published a little more than a decade ago on a DDR3-based system. Since then, we have had two generations of DRAM technology with proprietary mitigations. In this talk, I present our journey in understanding the security guarantees of these mitigations in DDR4 and DDR5 devices through significant platform building efforts, painstaking reverse engineering, and creative system-level techniques. The results are not encouraging; DRAM is as insecure as a decade ago while the cost of independent security analysis is growing beyond what academia can do. I finish with a brief discussion of possible paths forward.

Bio

Kaveh is an associate professor at ETH Zurich where he leads the COMSEC group. Next to defensive work, he has been involved in the discovery of many high-profile security vulnerabilities in commodity DRAM and CPU chips. He is a proud owner of five Pwnies and many best/distinguished paper awards, including at Oakland, USENIX Security and MICRO.

Photo © Giulia Marthaler / ETH Zurich

At the event, we present our new open bachelor’s thesis (and master’s thesis) topics and award prizes to excellent students.  

If you’re interested in joining us for your bachelor’s thesis in security, this is the best way to get an impression of our topics as well as how a bachelor’s thesis at ISEC works: You’ll hear about our research areas and current hot topics, our Bachelor@ISEC program where you can work on your thesis together with your fellow students in one of our offices if you like, and maybe you’ll get to know your supervisor while chatting along.

THE AWARDS:

ISEC Student Research Excellence Award: Students at ISEC who became co-authors of a scientific publication in the context of a thesis or project receive this award.

ISEC Bachelor Excellence Award: This award is for students majoring in “Information Security” at TU Graz and who have completed their bachelor’s degree with distinction at TU Graz. Application deadline: Oct 9th 2025!

The event will also be the kick-off lecture in Introduction to Scientific Working (ISW), where you will be able to choose your preferred topic!   

We are looking forward to meeting you!

Abstract

In this talk, we will discuss the modular interpretation of the Hessian transformation on elliptic curves. We begin by recalling some classical results concerning the action of the Hessian transforma-tion on the j-invariants and on the Hesse pencil, and we rephrase them in the context of the modu-lar curves X(1) and X(3). Building on the work of Mula, Pintore, and Taufer in the recent preprint (ArXiv:2407.17042), we lift the Hessian transformation up to maps on 16 different modular curves, in-cluding X(6), and analyse their effects on the associated moduli spaces. Finally, we give a numerical representation of Hessian map on the extended complex upper half-plane H∗. This talk is based on the speaker’s Master’s thesis supervised by Pintore, Taufer and Mula.

Bio

Riccardo Lolato — Master’s degree in Mathematics – Cryptography, Universita` degli Studi di Trento.

Photo provided by speaker

Abstract
Computing is bottlenecked by data. Large amounts of application data overwhelm the storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency, and scalability are bottlenecked by data movement. In this talk, we describe three major shortcomings of modern computers in terms of 1) dealing with data, 2) taking advantage of vast amounts of data, and 3) exploiting different semantic properties of application data. We argue that an intelligent computing architecture should be designed to handle data well. We posit that handling data well requires designing architectures based on three key principles: 1) data-centric, 2) data-driven, 3) data-aware. We give examples of how to exploit these principles to design a much more efficient and higher performance computing system. We especially discuss recent research that aims to fundamentally reduce memory latency and energy, and practically enable computation close to data, with at least two promising directions: 1) processing using memory, which exploits the fundamental operational properties of memory chips to perform massively-parallel computation in memory, with low-cost changes, 2) processing near memory, which integrates sophisticated additional processing capability in memory chips, the logic layer of 3D-stacked technologies, or memory controllers to enable near-memory computation with high memory bandwidth and low memory latency. We show both types of architectures can enable order(s) of magnitude improvements in performance and energy consumption of many important workloads, such as artificial intelligence, machine learning, graph analytics, database systems, video processing, climate modeling, genome analysis. We discuss how to enable adoption of such fundamentally more intelligent architectures, which are key to efficiency, performance, and sustainability. We conclude with some research opportunities in and guiding principles for future computing architecture and system designs.

An accompanying overview of modern memory-centric computing ideas & systems can be found at arxiv.org/pdf/2012.03112 (“A Modern Primer on Processing in Memory”, updated February 2025).

A shorter invited paper from IMW 2025 is at arxiv.org/pdf/2505.00458 (“Memory-Centric Computing: Solving Computing’s Memory Problem”, May 2025)

Bio

Onur Mutlu is a Professor of Computer Science at ETH Zurich. He previously held the William D. and Nancy W. Strecker Early Career Professorship at Carnegie Mellon University. His current research interests are in computer architecture, computing systems, hardware security, memory & storage systems, and bioinformatics, with a major focus on designing fundamentally energy-efficient, high-performance, and robust computing systems. Many techniques he, with his group and collaborators, has invented over the years have largely influenced industry and have been widely employed in commercial microprocessors and memory & storage systems used daily by hundreds of millions of people. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS degrees in Computer Engineering and Psychology from the University of Michigan, Ann Arbor. He started the Computer Architecture Group at Microsoft Research (2006-2009), and held product, research and visiting positions at Intel Corporation, Advanced Micro Devices, VMware, Google, and Stanford University. He received various honors for his research, including the 2025 IEEE Computer Society Harry H. Goode Memorial Award “for seminal contributions to computer architecture research and practice, especially in memory systems,” 2024 IFIP WG10.4 Jean-Claude Laprie Award in Dependable Computing (for the original RowHammer work), 2022 Persistent Impact Prize of the Non-Volatile Memory Systems Workshop (for original architectural work on Phase Change Memory), 2021 IEEE High Performance Computer Architecture Conference Test of Time Award (for the Runahead Execution work), 2020 IEEE Computer Society Edward J. McCluskey Technical Achievement Award, 2019 ACM SIGARCH Maurice Wilkes Award and more than thirty best paper, “Top Pick” paper, or test-of-time recognitions at various leading computer systems, architecture, and security venues. He is an ACM Fellow, IEEE Fellow, and an elected member of the Academy of Europe. He enjoys teaching, mentoring, and enabling & democratizing access to high-quality research and education. He has supervised 24 PhD graduates, many of whom received major dissertation awards, 15 postdoctoral trainees, and more than 60 Master’s and Bachelor’s students. His computer architecture and digital logic design course lectures and materials are freely available on YouTube (OnurMutluLectures & @CMUCompArch), and his research group makes a wide variety of open-source artifacts freely available online. For more information, please see his webpage.

Photo provided by speaker