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Debugging Formal Specifications Using Simple Counterstrategies
Könighofer R., Hofferek G., Bloem R.
Proceedings of 9th International Conference 2009 Formal Methods in Computer Aided Design FMCAD 2009
Formal Analysis of a TPM-Based Secrets Distribution and Storage Scheme
Tögl R., Hofferek G., Greimel K., Leung A., Phan R., Bloem R.
International Symposium on Trusted Computing (TrustCom 2008) Proceedings, in 9th ICYCS Conference Proceedings
Debugging Design Errors by Using Unsatisfiable Cores
Suelflow A., Fey G., Bloem R., Drechsler R.
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
Automatic Fault Localization for Property Checking
Fey G., Staber S., Bloem R., Drechsler R.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 27(6), 2008
Open Implication
Greimel K., Bloem R., Jobstmann B., Vardi M.
Automata, Languages and Programming - ICALP 2008
Using unsatisfiable cores to debug multiple design errors
Suelflow A., Fey G., Bloem R., Drechsler R.
GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
Symbolic Implementation of Alternating Automata
Bloem R., Cimatti A., Pill I., Roveri M.
International journal of foundations of computer science, Vol. 18(4), 2007
Specify, Compile, Run: Hardware from PSL
Bloem R., Galler S., Jobstmann B., Piterman N., Pnueli A., Weiglhofer M.
6th International Workshop on Compiler Optimization Meets Compiler Verification
Anzu: A Tool for Property Synthesis
Jobstmann B., Galler S., Weiglhofer M., Bloem R.
Proceedings of the 19th International Conference of Computer Aided Verification 2007
Interactive presentation: Automatic hardware synthesis from specifications: a case study
Bloem R., Galler S., Jobstmann B., Piterman N., Pnueli A., Weiglhofer M.
Proceedings of the conference on Design, automation and test in Europe
RAT: A Tool for the Formal Analysis of Requirements
Bloem R., Cavada R., Pill I., Roveri M., Tchaltsev A.
19th International Conference, CAV 2007, Berlin, Germany, July 3-7, 2007. Proceedings
Fault localization and correction with QBF
Staber S., Bloem R.
Theory and Applications of Satisfiability Testing – SAT 2007
Compositional SCC analysis for language emptiness
Wang C., Bloem R., Hachtel G., Ravi K., Somenzi F.
Formal Methods in System Design, Vol. 28(1), 2006
Symbolic implementation of alternating automata
Pill I., Bloem R., Cimatti A., Roveri M., Semprini S.
Implementation and application of automata
Formal analysis of hardware requirements
Pill I., Bloem R., Semprini S., Roveri M., Cimatti A., Cavada R.
Design Automation Conference
Repair of boolean programs with an application to C
Griesmayer A., Bloem R., Byron C.
Computer Aided Verification
Automated Fault Localization for C Programs
Griesmayer A., Staber S., Bloem R.
Workshop on Verification and Debugging
Game-based and simulation-based improvements for LTL synthesis
Jobstmann B., Bloem R.
Games in Design and Verification
Rat: A tool for formal analysis of requirements
Pill I., Bloem R., Cimatti A., Roveri M., Semprini S., Tchaltsev A.
European Conference on Artificial Intelligence
Automatic Fault Localization for Property Checking
Staber S., Fey G., Bloem R., Drechsler R.
Haifa Verification Conference