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High-Performance SIMD Software for Spielman Codes in Zero-Knowledge Proofs
Krieger F., Dobrouschek C., Hirner F., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2026(2), 2026
Attacking and Securing Hybrid Homomorphic Encryption Against Power Analysis
Aikata A., Czuprynko M., Musovic N., Salkić E., Sinha Roy S.
2026
Accelerating Hash-Based Polynomial Commitment Schemes with Linear Prover Time
Hirner F., Krieger F., Piber C., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(4), 2025
Stealthy Hardware Trojan Attacks on MQ-Based Post-Quantum Digital Signatures
Sinha Roy S., Aikata A., Mukherjee A.
LightSEC 2025
A Flexible Hardware Design Tool for Fast Fourier and Number-Theoretic Transformation Architectures
Krieger F., Hirner F., Mert A., Sinha Roy S.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
Simple Power Analysis Attack on SQIsign
Mukherjee A., Czuprynko M., Jacquemin D., Kutas P., Sinha Roy S.
Progress in Cryptology - AFRICACRYPT 2025
Correlation power analysis of LESS and CROSS
Czuprynko M., Mukherjee A., Sinha Roy S.
Progress in Cryptology - AFRICACRYPT 2025
Pasta on Edge: Cryptoprocessor for Hybrid Homomorphic Encryption
Aikata A., Sanz Sobrino D., Sinha Roy S.
2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings
Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing
Krieger F., Hirner F., Sinha Roy S.
2025 Design, Automation and Test in Europe Conference, DATE 2025 - Proceedings
OpenNTT - An Automated Toolchain for Compiling High-Performance NTT Accelerators in FHE
Krieger F., Hirner F., Mert A., Sinha Roy S.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design
Accelerating Isogeny Walks for VDF Evaluation
Jacquemin D., Mukherjee A., Mert A., Sinha Roy S.
IACR Communications in Crypology, Vol. 2(1), 2025
REED
Aikata A., Mert A., Kwon S., Deryabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(2), 2025
REED: Chiplet-Based Scalable Hardware Accelerator for Fully Homomorphic Encryption
Aikata A., Mert A., Kwon S., Deryabin M., Sinha Roy S.
IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025(2), 2025
Revisiting module-lattice based homomorphic encryption and application to secure-MPC
Mukherjee A., Sinha Roy S.
IACR Communications in Crypology, Vol. 2(2), 2025
Whipping the Multivariate-based MAYO Signature Scheme using Hardware Platforms
Hirner F., Streibl M., Krieger F., Mert A., Sinha Roy S.
CCS 2024 - Proceedings of the 2024 ACM SIGSAC Conference on Computer and Communications Security
Proteus: A Pipelined NTT Architecture Generator
Hirner F., Mert A., Sinha Roy S.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 32(7), 2024
REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography
Pagliarini S., Aikata A., Imran M., Sinha Roy S.
ACM AsiaCCS 2024 - Proceedings of the 19th ACM Asia Conference on Computer and Communications Security
Backdooring Post-Quantum Cryptography: Kleptographic Attacks on Lattice-based KEMs
Ravi P., Bhasin S., Chattopadhyay A., Aikata A., Sinha Roy S.
GLSVLSI 2024 - Proceedings of the Great Lakes Symposium on VLSI 2024