Algorithms to Hardware using High-Level Synthesis (SS2026)

Course Number 705034 | Sommersemester 2026

Content

This course introduces students to the fundamentals of transforming software algorithms into hardware architectures using high-level synthesis (HLS). Emphasizing data flow and control flow modelling, the course equips students with practical skills to design and explore hardware implementations of algorithmic specifications. The course targets bachelor's or master's students with a basic understanding of digital logic and programming. Specific content:
  • Introduction to hardware design and HLS concepts
  • Hardware-architectural aspects: Pipelining and parallel processing
  • Area, Performance, and Power/Energy tradeoffs
  • Modern memory hierarchies
  • Hardware-software co-design
  • Advanced architectures: Systolic arrays and streaming architectures

Material

We will publish all materials in this cloud folder. Links to individual resources (like slides) will be provided here:
Lecture:
Practicals:

Administrative Information

Previous Knowledge

Basic understanding of digital logic and programming.

Prerequisites Curriculum

See position in the curriculum

Objective

Know how to transform an algorithm into a hardware architecture. High-level Synthesis and toolchain. Design exploration.

Language

English

Teaching Method

Lectures and practicals will be in-person (1.5 hours lecture + 1 hour practical session).

How to get a grade

The grading is based on three practical assignments. Students will work on them individually.

Registration

https://online.tugraz.at/tug_online/ee/rest/pages/slc.tm.cp/course-registration/596979

Lecture Dates

Date Begin End Location Event Type Comment
2026/03/19 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/03/23 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/03/26 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/04/13 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/04/16 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/04/20 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/04/23 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/04/27 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/04/30 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/05/04 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/05/07 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/05/11 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/05/12 10:00 11:00 Seminarraum Abhaltung VU fix/
2026/05/18 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/05/21 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/06/01 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/06/02 10:00 11:00 Seminarraum Abhaltung VU fix/
2026/06/08 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/06/11 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/06/15 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/06/18 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/06/22 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/06/25 14:00 15:00 Seminarraum Abhaltung VU fix/
2026/06/29 12:30 14:00 Seminarraum Abhaltung VU fix/
2026/06/30 10:00 11:00 Seminarraum Abhaltung VU fix/

Lecturers

Sujoy Sinha Roy
Sujoy
Sinha Roy

Associate Professor

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Florian Hirner
Florian
Hirner

PhD Candidate

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Florian Krieger
Florian
Krieger

PhD Candidate

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