-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
-- Date        : Wed Dec 20 12:17:39 2023
-- Host        : t460sacm running 64-bit Ubuntu 20.04.6 LTS
-- Command     : write_vhdl -force -mode funcsim
--               /home/amert/Documents/Classes/Class-CryptEng-W2023/assignments/2/Sujoys_code/Assignment2/CryptoProcessor/CryptoProcessor_2022_23/project_1/project_1.srcs/sources_1/bd/cryptoprocessor/ip/cryptoprocessor_ComputeCoreWrapper_0_0/cryptoprocessor_ComputeCoreWrapper_0_0_sim_netlist.vhdl
-- Design      : cryptoprocessor_ComputeCoreWrapper_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv is
  port (
    en : in STD_LOGIC;
    bit_out : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv : entity is "ro_3inv";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv : entity is "true";
end cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv is
  signal inv_chain : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of inv_chain : signal is std.standard.true;
begin
  bit_out <= inv_chain(2);
inv_chain_inferred_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(1),
      O => inv_chain(2)
    );
inv_chain_inferred_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(0),
      O => inv_chain(1)
    );
inv_chain_inferred_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => en,
      I1 => inv_chain(2),
      O => inv_chain(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv is
  port (
    en : in STD_LOGIC;
    bit_out : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv : entity is "ro_5inv";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv : entity is "true";
end cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv is
  signal inv_chain : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of inv_chain : signal is std.standard.true;
begin
  bit_out <= inv_chain(4);
inv_chain_inferred_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(3),
      O => inv_chain(4)
    );
inv_chain_inferred_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(2),
      O => inv_chain(3)
    );
inv_chain_inferred_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(1),
      O => inv_chain(2)
    );
inv_chain_inferred_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => inv_chain(0),
      O => inv_chain(1)
    );
inv_chain_inferred_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => en,
      I1 => inv_chain(4),
      O => inv_chain(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test is
  port (
    stat_error : out STD_LOGIC;
    \command_reg0_reg[0]\ : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    en : out STD_LOGIC;
    error_reg : out STD_LOGIC;
    rng_ready : in STD_LOGIC;
    clk : in STD_LOGIC;
    CO : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    error_trng_reg_reg : in STD_LOGIC;
    enable_TRO_for_bitgen : in STD_LOGIC;
    rng_reg : in STD_LOGIC_VECTOR ( 63 downto 0 );
    error_trng : in STD_LOGIC;
    error_trng_reg_reg_0 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test : entity is "statistical_test";
end cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^command_reg0_reg[0]\ : STD_LOGIC;
  signal enable_TRO_for_statbits : STD_LOGIC;
  signal enable_TRO_i_1_n_0 : STD_LOGIC;
  signal \i__carry__0_i_10_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_11_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_12_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_13_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_14_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_15_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_16_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_17_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_18_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_19_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_1_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_20_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_21_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_22_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_23_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_24_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_25_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_26_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_27_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_28_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_29_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_4_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_5_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_6_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_7_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_8_n_0\ : STD_LOGIC;
  signal \i__carry__0_i_9_n_0\ : STD_LOGIC;
  signal \i__carry_i_10_n_0\ : STD_LOGIC;
  signal \i__carry_i_11_n_0\ : STD_LOGIC;
  signal \i__carry_i_12_n_0\ : STD_LOGIC;
  signal \i__carry_i_13_n_0\ : STD_LOGIC;
  signal \i__carry_i_14_n_0\ : STD_LOGIC;
  signal \i__carry_i_15_n_0\ : STD_LOGIC;
  signal \i__carry_i_16_n_0\ : STD_LOGIC;
  signal \i__carry_i_17_n_0\ : STD_LOGIC;
  signal \i__carry_i_18_n_0\ : STD_LOGIC;
  signal \i__carry_i_19_n_0\ : STD_LOGIC;
  signal \i__carry_i_1_n_0\ : STD_LOGIC;
  signal \i__carry_i_20_n_0\ : STD_LOGIC;
  signal \i__carry_i_21_n_0\ : STD_LOGIC;
  signal \i__carry_i_22_n_0\ : STD_LOGIC;
  signal \i__carry_i_23_n_0\ : STD_LOGIC;
  signal \i__carry_i_24_n_0\ : STD_LOGIC;
  signal \i__carry_i_25_n_0\ : STD_LOGIC;
  signal \i__carry_i_26_n_0\ : STD_LOGIC;
  signal \i__carry_i_27_n_0\ : STD_LOGIC;
  signal \i__carry_i_28_n_0\ : STD_LOGIC;
  signal \i__carry_i_29_n_0\ : STD_LOGIC;
  signal \i__carry_i_2_n_0\ : STD_LOGIC;
  signal \i__carry_i_30_n_0\ : STD_LOGIC;
  signal \i__carry_i_31_n_0\ : STD_LOGIC;
  signal \i__carry_i_32_n_0\ : STD_LOGIC;
  signal \i__carry_i_33_n_0\ : STD_LOGIC;
  signal \i__carry_i_34_n_0\ : STD_LOGIC;
  signal \i__carry_i_35_n_0\ : STD_LOGIC;
  signal \i__carry_i_36_n_0\ : STD_LOGIC;
  signal \i__carry_i_37_n_0\ : STD_LOGIC;
  signal \i__carry_i_38_n_0\ : STD_LOGIC;
  signal \i__carry_i_39_n_0\ : STD_LOGIC;
  signal \i__carry_i_3_n_0\ : STD_LOGIC;
  signal \i__carry_i_40_n_0\ : STD_LOGIC;
  signal \i__carry_i_41_n_0\ : STD_LOGIC;
  signal \i__carry_i_42_n_0\ : STD_LOGIC;
  signal \i__carry_i_43_n_0\ : STD_LOGIC;
  signal \i__carry_i_44_n_0\ : STD_LOGIC;
  signal \i__carry_i_45_n_0\ : STD_LOGIC;
  signal \i__carry_i_46_n_0\ : STD_LOGIC;
  signal \i__carry_i_47_n_0\ : STD_LOGIC;
  signal \i__carry_i_48_n_0\ : STD_LOGIC;
  signal \i__carry_i_49_n_0\ : STD_LOGIC;
  signal \i__carry_i_4_n_0\ : STD_LOGIC;
  signal \i__carry_i_50_n_0\ : STD_LOGIC;
  signal \i__carry_i_51_n_0\ : STD_LOGIC;
  signal \i__carry_i_52_n_0\ : STD_LOGIC;
  signal \i__carry_i_53_n_0\ : STD_LOGIC;
  signal \i__carry_i_54_n_0\ : STD_LOGIC;
  signal \i__carry_i_55_n_0\ : STD_LOGIC;
  signal \i__carry_i_56_n_0\ : STD_LOGIC;
  signal \i__carry_i_57_n_0\ : STD_LOGIC;
  signal \i__carry_i_58_n_0\ : STD_LOGIC;
  signal \i__carry_i_59_n_0\ : STD_LOGIC;
  signal \i__carry_i_5_n_0\ : STD_LOGIC;
  signal \i__carry_i_60_n_0\ : STD_LOGIC;
  signal \i__carry_i_61_n_0\ : STD_LOGIC;
  signal \i__carry_i_62_n_0\ : STD_LOGIC;
  signal \i__carry_i_63_n_0\ : STD_LOGIC;
  signal \i__carry_i_64_n_0\ : STD_LOGIC;
  signal \i__carry_i_65_n_0\ : STD_LOGIC;
  signal \i__carry_i_66_n_0\ : STD_LOGIC;
  signal \i__carry_i_67_n_0\ : STD_LOGIC;
  signal \i__carry_i_68_n_0\ : STD_LOGIC;
  signal \i__carry_i_69_n_0\ : STD_LOGIC;
  signal \i__carry_i_6_n_0\ : STD_LOGIC;
  signal \i__carry_i_70_n_0\ : STD_LOGIC;
  signal \i__carry_i_71_n_0\ : STD_LOGIC;
  signal \i__carry_i_72_n_0\ : STD_LOGIC;
  signal \i__carry_i_73_n_0\ : STD_LOGIC;
  signal \i__carry_i_74_n_0\ : STD_LOGIC;
  signal \i__carry_i_75_n_0\ : STD_LOGIC;
  signal \i__carry_i_7_n_0\ : STD_LOGIC;
  signal \i__carry_i_8_n_0\ : STD_LOGIC;
  signal \i__carry_i_9_n_0\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__0_n_0\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__1_n_0\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__2_n_0\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__2_n_1\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__3_n_1\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__3_n_2\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry__3_n_3\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry_n_0\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \num_of_1s0_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[0]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[10]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[11]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[12]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[13]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[14]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[15]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[16]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[17]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[18]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[19]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[1]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[2]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[3]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[4]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[5]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[6]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[7]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[8]\ : STD_LOGIC;
  signal \num_of_1s_reg_n_0_[9]\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal rng_ready_d0 : STD_LOGIC;
  signal rng_ready_d1 : STD_LOGIC;
  signal rng_word_counter0 : STD_LOGIC;
  signal \rng_word_counter[0]_i_4_n_0\ : STD_LOGIC;
  signal \rng_word_counter[0]_i_5_n_0\ : STD_LOGIC;
  signal \rng_word_counter[0]_i_6_n_0\ : STD_LOGIC;
  signal \rng_word_counter[0]_i_7_n_0\ : STD_LOGIC;
  signal \rng_word_counter[0]_i_8_n_0\ : STD_LOGIC;
  signal rng_word_counter_reg : STD_LOGIC_VECTOR ( 19 downto 0 );
  signal \rng_word_counter_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_1\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_2\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_3\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_4\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_5\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_6\ : STD_LOGIC;
  signal \rng_word_counter_reg[0]_i_2_n_7\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \rng_word_counter_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \rng_word_counter_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \rng_word_counter_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \rng_word_counter_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal stat_done : STD_LOGIC;
  signal \^stat_error\ : STD_LOGIC;
  signal stat_error_i_1_n_0 : STD_LOGIC;
  signal stat_error_i_2_n_0 : STD_LOGIC;
  signal stat_error_i_3_n_0 : STD_LOGIC;
  signal stat_error_i_4_n_0 : STD_LOGIC;
  signal stat_error_i_5_n_0 : STD_LOGIC;
  signal stat_error_i_6_n_0 : STD_LOGIC;
  signal stat_error_i_7_n_0 : STD_LOGIC;
  signal stat_error_i_8_n_0 : STD_LOGIC;
  signal stat_trng_rst : STD_LOGIC;
  signal \NLW_num_of_1s0_inferred__0/i__carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_rng_word_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \i__carry__0_i_10\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \i__carry__0_i_13\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \i__carry__0_i_14\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \i__carry__0_i_16\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \i__carry__0_i_17\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \i__carry__0_i_18\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \i__carry__0_i_19\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \i__carry__0_i_20\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \i__carry__0_i_21\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \i__carry__0_i_27\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \i__carry__0_i_6\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \i__carry__0_i_8\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \i__carry_i_10\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \i__carry_i_11\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \i__carry_i_12\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \i__carry_i_13\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \i__carry_i_14\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \i__carry_i_16\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \i__carry_i_17\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \i__carry_i_18\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \i__carry_i_19\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \i__carry_i_20\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \i__carry_i_22\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \i__carry_i_23\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \i__carry_i_24\ : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of \i__carry_i_26\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \i__carry_i_27\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \i__carry_i_29\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \i__carry_i_31\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \i__carry_i_32\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \i__carry_i_33\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \i__carry_i_35\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \i__carry_i_40\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \i__carry_i_41\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \i__carry_i_44\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \i__carry_i_45\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \i__carry_i_47\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \i__carry_i_48\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \i__carry_i_49\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \i__carry_i_5\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \i__carry_i_50\ : label is "soft_lutpair16";
  attribute SOFT_HLUTNM of \i__carry_i_51\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \i__carry_i_52\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \i__carry_i_55\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \i__carry_i_57\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \i__carry_i_58\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \i__carry_i_6\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \i__carry_i_60\ : label is "soft_lutpair19";
  attribute SOFT_HLUTNM of \i__carry_i_61\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \i__carry_i_63\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \i__carry_i_64\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \i__carry_i_69\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \i__carry_i_7\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \i__carry_i_70\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \i__carry_i_71\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \i__carry_i_9\ : label is "soft_lutpair24";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of \num_of_1s0_inferred__0/i__carry\ : label is 35;
  attribute ADDER_THRESHOLD of \num_of_1s0_inferred__0/i__carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \num_of_1s0_inferred__0/i__carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of \num_of_1s0_inferred__0/i__carry__2\ : label is 35;
  attribute ADDER_THRESHOLD of \num_of_1s0_inferred__0/i__carry__3\ : label is 35;
  attribute ADDER_THRESHOLD of \rng_word_counter_reg[0]_i_2\ : label is 11;
  attribute ADDER_THRESHOLD of \rng_word_counter_reg[12]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \rng_word_counter_reg[16]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \rng_word_counter_reg[4]_i_1\ : label is 11;
  attribute ADDER_THRESHOLD of \rng_word_counter_reg[8]_i_1\ : label is 11;
  attribute SOFT_HLUTNM of stat_error_i_6 : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of stat_error_i_8 : label is "soft_lutpair2";
begin
  E(0) <= \^e\(0);
  \command_reg0_reg[0]\ <= \^command_reg0_reg[0]\;
  stat_error <= \^stat_error\;
\FSM_sequential_state[1]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EA2A"
    )
        port map (
      I0 => CO(0),
      I1 => Q(0),
      I2 => error_trng_reg_reg,
      I3 => stat_done,
      O => \^command_reg0_reg[0]\
    );
TRO_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EA2A"
    )
        port map (
      I0 => enable_TRO_for_bitgen,
      I1 => Q(0),
      I2 => error_trng_reg_reg,
      I3 => enable_TRO_for_statbits,
      O => en
    );
enable_TRO_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000100000000000"
    )
        port map (
      I0 => stat_done,
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => Q(0),
      O => enable_TRO_i_1_n_0
    );
enable_TRO_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => enable_TRO_i_1_n_0,
      Q => enable_TRO_for_statbits,
      R => '0'
    );
error_trng_reg_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8B88"
    )
        port map (
      I0 => error_trng,
      I1 => \^command_reg0_reg[0]\,
      I2 => error_trng_reg_reg_0,
      I3 => D(0),
      O => error_reg
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA6"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[6]\,
      I1 => \i__carry__0_i_4_n_0\,
      I2 => \i__carry__0_i_5_n_0\,
      I3 => \i__carry__0_i_6_n_0\,
      O => \i__carry__0_i_1_n_0\
    );
\i__carry__0_i_10\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \i__carry_i_58_n_0\,
      I1 => \i__carry_i_59_n_0\,
      I2 => \i__carry_i_60_n_0\,
      O => \i__carry__0_i_10_n_0\
    );
\i__carry__0_i_11\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry__0_i_16_n_0\,
      I1 => \i__carry__0_i_17_n_0\,
      I2 => \i__carry__0_i_18_n_0\,
      O => \i__carry__0_i_11_n_0\
    );
\i__carry__0_i_12\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8E8E8E718E717171"
    )
        port map (
      I0 => \i__carry__0_i_18_n_0\,
      I1 => \i__carry__0_i_17_n_0\,
      I2 => \i__carry__0_i_16_n_0\,
      I3 => \i__carry__0_i_21_n_0\,
      I4 => \i__carry__0_i_20_n_0\,
      I5 => \i__carry__0_i_19_n_0\,
      O => \i__carry__0_i_12_n_0\
    );
\i__carry__0_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96FF0096"
    )
        port map (
      I0 => \i__carry__0_i_20_n_0\,
      I1 => \i__carry__0_i_21_n_0\,
      I2 => \i__carry__0_i_19_n_0\,
      I3 => \i__carry_i_46_n_0\,
      I4 => \i__carry_i_45_n_0\,
      O => \i__carry__0_i_13_n_0\
    );
\i__carry__0_i_14\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry_i_20_n_0\,
      I1 => \i__carry_i_21_n_0\,
      I2 => \i__carry_i_22_n_0\,
      O => \i__carry__0_i_14_n_0\
    );
\i__carry__0_i_15\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8E"
    )
        port map (
      I0 => \i__carry_i_26_n_0\,
      I1 => \i__carry_i_25_n_0\,
      I2 => \i__carry_i_24_n_0\,
      O => \i__carry__0_i_15_n_0\
    );
\i__carry__0_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E800FFE8"
    )
        port map (
      I0 => rng_reg(8),
      I1 => rng_reg(7),
      I2 => rng_reg(9),
      I3 => \i__carry__0_i_22_n_0\,
      I4 => \i__carry__0_i_23_n_0\,
      O => \i__carry__0_i_16_n_0\
    );
\i__carry__0_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11171777"
    )
        port map (
      I0 => \i__carry__0_i_24_n_0\,
      I1 => \i__carry__0_i_25_n_0\,
      I2 => rng_reg(18),
      I3 => rng_reg(17),
      I4 => rng_reg(16),
      O => \i__carry__0_i_17_n_0\
    );
\i__carry__0_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888E8EEE"
    )
        port map (
      I0 => \i__carry__0_i_26_n_0\,
      I1 => \i__carry__0_i_27_n_0\,
      I2 => rng_reg(27),
      I3 => rng_reg(26),
      I4 => rng_reg(25),
      O => \i__carry__0_i_18_n_0\
    );
\i__carry__0_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"888A8AAA"
    )
        port map (
      I0 => \i__carry__0_i_28_n_0\,
      I1 => \i__carry__0_i_29_n_0\,
      I2 => rng_reg(36),
      I3 => rng_reg(35),
      I4 => rng_reg(34),
      O => \i__carry__0_i_19_n_0\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"655965596559AAA9"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[5]\,
      I1 => \i__carry__0_i_4_n_0\,
      I2 => \i__carry__0_i_5_n_0\,
      I3 => \i__carry__0_i_6_n_0\,
      I4 => \i__carry__0_i_7_n_0\,
      I5 => \i__carry__0_i_8_n_0\,
      O => \i__carry__0_i_2_n_0\
    );
\i__carry__0_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11171777"
    )
        port map (
      I0 => \i__carry_i_64_n_0\,
      I1 => \i__carry_i_63_n_0\,
      I2 => rng_reg(52),
      I3 => rng_reg(53),
      I4 => rng_reg(54),
      O => \i__carry__0_i_20_n_0\
    );
\i__carry__0_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"222B2BBB"
    )
        port map (
      I0 => \i__carry_i_62_n_0\,
      I1 => \i__carry_i_61_n_0\,
      I2 => rng_reg(45),
      I3 => rng_reg(43),
      I4 => rng_reg(44),
      O => \i__carry__0_i_21_n_0\
    );
\i__carry__0_i_22\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(4),
      I1 => rng_reg(6),
      I2 => rng_reg(5),
      O => \i__carry__0_i_22_n_0\
    );
\i__carry__0_i_23\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(2),
      I1 => rng_reg(1),
      I2 => rng_reg(3),
      O => \i__carry__0_i_23_n_0\
    );
\i__carry__0_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(10),
      I1 => rng_reg(12),
      I2 => rng_reg(11),
      O => \i__carry__0_i_24_n_0\
    );
\i__carry__0_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(15),
      I1 => rng_reg(14),
      I2 => rng_reg(13),
      O => \i__carry__0_i_25_n_0\
    );
\i__carry__0_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(24),
      I1 => rng_reg(23),
      I2 => rng_reg(22),
      O => \i__carry__0_i_26_n_0\
    );
\i__carry__0_i_27\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(20),
      I1 => rng_reg(19),
      I2 => rng_reg(21),
      O => \i__carry__0_i_27_n_0\
    );
\i__carry__0_i_28\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"171717FF17FFFFFF"
    )
        port map (
      I0 => rng_reg(30),
      I1 => rng_reg(28),
      I2 => rng_reg(29),
      I3 => rng_reg(31),
      I4 => rng_reg(32),
      I5 => rng_reg(33),
      O => \i__carry__0_i_28_n_0\
    );
\i__carry__0_i_29\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001700171717"
    )
        port map (
      I0 => rng_reg(30),
      I1 => rng_reg(28),
      I2 => rng_reg(29),
      I3 => rng_reg(31),
      I4 => rng_reg(32),
      I5 => rng_reg(33),
      O => \i__carry__0_i_29_n_0\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[4]\,
      I1 => \i__carry__0_i_6_n_0\,
      I2 => \i__carry__0_i_8_n_0\,
      I3 => \i__carry__0_i_7_n_0\,
      I4 => \i__carry__0_i_5_n_0\,
      O => \i__carry__0_i_3_n_0\
    );
\i__carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D4FF0000"
    )
        port map (
      I0 => \i__carry__0_i_9_n_0\,
      I1 => \i__carry__0_i_10_n_0\,
      I2 => \i__carry__0_i_11_n_0\,
      I3 => \i__carry__0_i_12_n_0\,
      I4 => \i__carry__0_i_7_n_0\,
      I5 => \i__carry__0_i_13_n_0\,
      O => \i__carry__0_i_4_n_0\
    );
\i__carry__0_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AE8AEFAE"
    )
        port map (
      I0 => \i__carry_i_8_n_0\,
      I1 => \i__carry_i_5_n_0\,
      I2 => \i__carry__0_i_14_n_0\,
      I3 => \i__carry_i_19_n_0\,
      I4 => \i__carry_i_6_n_0\,
      O => \i__carry__0_i_5_n_0\
    );
\i__carry__0_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD4D400"
    )
        port map (
      I0 => \i__carry_i_20_n_0\,
      I1 => \i__carry_i_22_n_0\,
      I2 => \i__carry_i_21_n_0\,
      I3 => \i__carry__0_i_15_n_0\,
      I4 => \i__carry_i_23_n_0\,
      O => \i__carry__0_i_6_n_0\
    );
\i__carry__0_i_7\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000002B002B2B2B"
    )
        port map (
      I0 => \i__carry__0_i_16_n_0\,
      I1 => \i__carry__0_i_17_n_0\,
      I2 => \i__carry__0_i_18_n_0\,
      I3 => \i__carry__0_i_19_n_0\,
      I4 => \i__carry__0_i_20_n_0\,
      I5 => \i__carry__0_i_21_n_0\,
      O => \i__carry__0_i_7_n_0\
    );
\i__carry__0_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00D4D4FF"
    )
        port map (
      I0 => \i__carry__0_i_9_n_0\,
      I1 => \i__carry__0_i_10_n_0\,
      I2 => \i__carry__0_i_11_n_0\,
      I3 => \i__carry__0_i_13_n_0\,
      I4 => \i__carry__0_i_12_n_0\,
      O => \i__carry__0_i_8_n_0\
    );
\i__carry__0_i_9\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \i__carry_i_27_n_0\,
      I1 => \i__carry_i_28_n_0\,
      I2 => \i__carry_i_29_n_0\,
      O => \i__carry__0_i_9_n_0\
    );
\i__carry_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D42B2BD42BD4D42B"
    )
        port map (
      I0 => \i__carry_i_5_n_0\,
      I1 => \i__carry_i_6_n_0\,
      I2 => \i__carry_i_7_n_0\,
      I3 => \num_of_1s_reg_n_0_[3]\,
      I4 => \i__carry_i_8_n_0\,
      I5 => \i__carry_i_9_n_0\,
      O => \i__carry_i_1_n_0\
    );
\i__carry_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_27_n_0\,
      I1 => \i__carry_i_28_n_0\,
      I2 => \i__carry_i_29_n_0\,
      I3 => \i__carry_i_30_n_0\,
      I4 => \i__carry_i_31_n_0\,
      O => \i__carry_i_10_n_0\
    );
\i__carry_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_32_n_0\,
      I1 => \i__carry_i_33_n_0\,
      I2 => \i__carry_i_34_n_0\,
      I3 => \i__carry_i_35_n_0\,
      I4 => \i__carry_i_36_n_0\,
      O => \i__carry_i_11_n_0\
    );
\i__carry_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2BB2B22B"
    )
        port map (
      I0 => \i__carry_i_37_n_0\,
      I1 => \i__carry_i_38_n_0\,
      I2 => rng_reg(2),
      I3 => rng_reg(1),
      I4 => rng_reg(3),
      O => \i__carry_i_12_n_0\
    );
\i__carry_i_13\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2B"
    )
        port map (
      I0 => \i__carry_i_16_n_0\,
      I1 => \i__carry_i_15_n_0\,
      I2 => \i__carry_i_17_n_0\,
      O => \i__carry_i_13_n_0\
    );
\i__carry_i_14\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0069"
    )
        port map (
      I0 => \i__carry_i_17_n_0\,
      I1 => \i__carry_i_16_n_0\,
      I2 => \i__carry_i_15_n_0\,
      I3 => \i__carry_i_18_n_0\,
      O => \i__carry_i_14_n_0\
    );
\i__carry_i_15\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => \i__carry_i_39_n_0\,
      I1 => rng_reg(28),
      I2 => rng_reg(29),
      I3 => rng_reg(30),
      I4 => \i__carry_i_40_n_0\,
      I5 => \i__carry_i_41_n_0\,
      O => \i__carry_i_15_n_0\
    );
\i__carry_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => rng_reg(50),
      I1 => rng_reg(51),
      I2 => rng_reg(49),
      I3 => \i__carry_i_42_n_0\,
      I4 => \i__carry_i_43_n_0\,
      O => \i__carry_i_16_n_0\
    );
\i__carry_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => rng_reg(59),
      I1 => rng_reg(58),
      I2 => rng_reg(60),
      I3 => \i__carry_i_44_n_0\,
      I4 => rng_reg(0),
      O => \i__carry_i_17_n_0\
    );
\i__carry_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_37_n_0\,
      I1 => rng_reg(3),
      I2 => rng_reg(1),
      I3 => rng_reg(2),
      I4 => \i__carry_i_38_n_0\,
      O => \i__carry_i_18_n_0\
    );
\i__carry_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF969600"
    )
        port map (
      I0 => \i__carry_i_27_n_0\,
      I1 => \i__carry_i_28_n_0\,
      I2 => \i__carry_i_29_n_0\,
      I3 => \i__carry_i_30_n_0\,
      I4 => \i__carry_i_31_n_0\,
      O => \i__carry_i_19_n_0\
    );
\i__carry_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9669"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[2]\,
      I1 => \i__carry_i_6_n_0\,
      I2 => \i__carry_i_7_n_0\,
      I3 => \i__carry_i_5_n_0\,
      O => \i__carry_i_2_n_0\
    );
\i__carry_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_45_n_0\,
      I1 => \i__carry_i_46_n_0\,
      I2 => \i__carry_i_47_n_0\,
      I3 => \i__carry_i_25_n_0\,
      I4 => \i__carry_i_26_n_0\,
      O => \i__carry_i_20_n_0\
    );
\i__carry_i_21\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry__0_i_11_n_0\,
      I1 => \i__carry__0_i_10_n_0\,
      I2 => \i__carry__0_i_9_n_0\,
      O => \i__carry_i_21_n_0\
    );
\i__carry_i_22\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"009696FF"
    )
        port map (
      I0 => \i__carry_i_32_n_0\,
      I1 => \i__carry_i_33_n_0\,
      I2 => \i__carry_i_34_n_0\,
      I3 => \i__carry_i_35_n_0\,
      I4 => \i__carry_i_36_n_0\,
      O => \i__carry_i_22_n_0\
    );
\i__carry_i_23\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2BD4D42B"
    )
        port map (
      I0 => \i__carry__0_i_9_n_0\,
      I1 => \i__carry__0_i_10_n_0\,
      I2 => \i__carry__0_i_11_n_0\,
      I3 => \i__carry__0_i_12_n_0\,
      I4 => \i__carry__0_i_13_n_0\,
      O => \i__carry_i_23_n_0\
    );
\i__carry_i_24\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry_i_47_n_0\,
      I1 => \i__carry_i_46_n_0\,
      I2 => \i__carry_i_45_n_0\,
      O => \i__carry_i_24_n_0\
    );
\i__carry_i_25\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2B"
    )
        port map (
      I0 => \i__carry_i_32_n_0\,
      I1 => \i__carry_i_33_n_0\,
      I2 => \i__carry_i_34_n_0\,
      O => \i__carry_i_25_n_0\
    );
\i__carry_i_26\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => \i__carry_i_48_n_0\,
      I1 => \i__carry_i_49_n_0\,
      I2 => \i__carry_i_50_n_0\,
      O => \i__carry_i_26_n_0\
    );
\i__carry_i_27\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF696900"
    )
        port map (
      I0 => rng_reg(45),
      I1 => rng_reg(43),
      I2 => rng_reg(44),
      I3 => \i__carry_i_51_n_0\,
      I4 => \i__carry_i_52_n_0\,
      O => \i__carry_i_27_n_0\
    );
\i__carry_i_28\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2882AAAA"
    )
        port map (
      I0 => \i__carry_i_53_n_0\,
      I1 => rng_reg(30),
      I2 => rng_reg(29),
      I3 => rng_reg(28),
      I4 => \i__carry_i_54_n_0\,
      O => \i__carry_i_28_n_0\
    );
\i__carry_i_29\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2BB2B22B"
    )
        port map (
      I0 => \i__carry_i_55_n_0\,
      I1 => \i__carry_i_56_n_0\,
      I2 => rng_reg(39),
      I3 => rng_reg(37),
      I4 => rng_reg(38),
      O => \i__carry_i_29_n_0\
    );
\i__carry_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6996966996696996"
    )
        port map (
      I0 => \i__carry_i_10_n_0\,
      I1 => \i__carry_i_11_n_0\,
      I2 => \i__carry_i_12_n_0\,
      I3 => \num_of_1s_reg_n_0_[1]\,
      I4 => \i__carry_i_13_n_0\,
      I5 => \i__carry_i_14_n_0\,
      O => \i__carry_i_3_n_0\
    );
\i__carry_i_30\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A99595A995A9A995"
    )
        port map (
      I0 => \i__carry_i_57_n_0\,
      I1 => rng_reg(0),
      I2 => \i__carry_i_44_n_0\,
      I3 => rng_reg(59),
      I4 => rng_reg(58),
      I5 => rng_reg(60),
      O => \i__carry_i_30_n_0\
    );
\i__carry_i_31\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry_i_58_n_0\,
      I1 => \i__carry_i_59_n_0\,
      I2 => \i__carry_i_60_n_0\,
      O => \i__carry_i_31_n_0\
    );
\i__carry_i_32\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => rng_reg(44),
      I1 => rng_reg(43),
      I2 => rng_reg(45),
      I3 => \i__carry_i_61_n_0\,
      I4 => \i__carry_i_62_n_0\,
      O => \i__carry_i_32_n_0\
    );
\i__carry_i_33\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"99969666"
    )
        port map (
      I0 => \i__carry_i_63_n_0\,
      I1 => \i__carry_i_64_n_0\,
      I2 => rng_reg(54),
      I3 => rng_reg(53),
      I4 => rng_reg(52),
      O => \i__carry_i_33_n_0\
    );
\i__carry_i_34\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"17E8"
    )
        port map (
      I0 => rng_reg(34),
      I1 => rng_reg(35),
      I2 => rng_reg(36),
      I3 => \i__carry_i_65_n_0\,
      O => \i__carry_i_34_n_0\
    );
\i__carry_i_35\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry_i_50_n_0\,
      I1 => \i__carry_i_49_n_0\,
      I2 => \i__carry_i_48_n_0\,
      O => \i__carry_i_35_n_0\
    );
\i__carry_i_36\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF966996690000"
    )
        port map (
      I0 => \i__carry_i_39_n_0\,
      I1 => rng_reg(28),
      I2 => rng_reg(29),
      I3 => rng_reg(30),
      I4 => \i__carry_i_41_n_0\,
      I5 => \i__carry_i_40_n_0\,
      O => \i__carry_i_36_n_0\
    );
\i__carry_i_37\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6996"
    )
        port map (
      I0 => rng_reg(20),
      I1 => rng_reg(19),
      I2 => rng_reg(21),
      I3 => \i__carry_i_66_n_0\,
      O => \i__carry_i_37_n_0\
    );
\i__carry_i_38\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9669"
    )
        port map (
      I0 => rng_reg(7),
      I1 => rng_reg(8),
      I2 => rng_reg(9),
      I3 => \i__carry_i_67_n_0\,
      O => \i__carry_i_38_n_0\
    );
\i__carry_i_39\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => rng_reg(25),
      I1 => rng_reg(26),
      I2 => rng_reg(27),
      I3 => rng_reg(22),
      I4 => rng_reg(23),
      I5 => rng_reg(24),
      O => \i__carry_i_39_n_0\
    );
\i__carry_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_15_n_0\,
      I1 => \i__carry_i_16_n_0\,
      I2 => \i__carry_i_17_n_0\,
      I3 => \num_of_1s_reg_n_0_[0]\,
      I4 => \i__carry_i_18_n_0\,
      O => \i__carry_i_4_n_0\
    );
\i__carry_i_40\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"69969669"
    )
        port map (
      I0 => \i__carry_i_55_n_0\,
      I1 => \i__carry_i_56_n_0\,
      I2 => rng_reg(38),
      I3 => rng_reg(37),
      I4 => rng_reg(39),
      O => \i__carry_i_40_n_0\
    );
\i__carry_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"96696996"
    )
        port map (
      I0 => \i__carry_i_51_n_0\,
      I1 => \i__carry_i_52_n_0\,
      I2 => rng_reg(44),
      I3 => rng_reg(43),
      I4 => rng_reg(45),
      O => \i__carry_i_41_n_0\
    );
\i__carry_i_42\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rng_reg(57),
      I1 => rng_reg(55),
      I2 => rng_reg(56),
      O => \i__carry_i_42_n_0\
    );
\i__carry_i_43\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rng_reg(52),
      I1 => rng_reg(54),
      I2 => rng_reg(53),
      O => \i__carry_i_43_n_0\
    );
\i__carry_i_44\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rng_reg(63),
      I1 => rng_reg(61),
      I2 => rng_reg(62),
      O => \i__carry_i_44_n_0\
    );
\i__carry_i_45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF171700"
    )
        port map (
      I0 => rng_reg(56),
      I1 => rng_reg(55),
      I2 => rng_reg(57),
      I3 => \i__carry_i_68_n_0\,
      I4 => \i__carry_i_69_n_0\,
      O => \i__carry_i_45_n_0\
    );
\i__carry_i_46\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8E8E8E008E000000"
    )
        port map (
      I0 => \i__carry_i_43_n_0\,
      I1 => \i__carry_i_42_n_0\,
      I2 => \i__carry_i_70_n_0\,
      I3 => rng_reg(0),
      I4 => \i__carry_i_44_n_0\,
      I5 => \i__carry_i_71_n_0\,
      O => \i__carry_i_46_n_0\
    );
\i__carry_i_47\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => \i__carry__0_i_19_n_0\,
      I1 => \i__carry__0_i_21_n_0\,
      I2 => \i__carry__0_i_20_n_0\,
      O => \i__carry_i_47_n_0\
    );
\i__carry_i_48\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66696999"
    )
        port map (
      I0 => \i__carry__0_i_23_n_0\,
      I1 => \i__carry__0_i_22_n_0\,
      I2 => rng_reg(9),
      I3 => rng_reg(7),
      I4 => rng_reg(8),
      O => \i__carry_i_48_n_0\
    );
\i__carry_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => rng_reg(16),
      I1 => rng_reg(17),
      I2 => rng_reg(18),
      I3 => \i__carry__0_i_25_n_0\,
      I4 => \i__carry__0_i_24_n_0\,
      O => \i__carry_i_49_n_0\
    );
\i__carry_i_5\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => \i__carry_i_11_n_0\,
      I1 => \i__carry_i_10_n_0\,
      I2 => \i__carry_i_12_n_0\,
      O => \i__carry_i_5_n_0\
    );
\i__carry_i_50\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E81717E8"
    )
        port map (
      I0 => rng_reg(25),
      I1 => rng_reg(26),
      I2 => rng_reg(27),
      I3 => \i__carry__0_i_27_n_0\,
      I4 => \i__carry__0_i_26_n_0\,
      O => \i__carry_i_50_n_0\
    );
\i__carry_i_51\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => rng_reg(40),
      I1 => rng_reg(41),
      I2 => rng_reg(42),
      O => \i__carry_i_51_n_0\
    );
\i__carry_i_52\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => rng_reg(46),
      I1 => rng_reg(47),
      I2 => rng_reg(48),
      O => \i__carry_i_52_n_0\
    );
\i__carry_i_53\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69FFFF69FF6969FF"
    )
        port map (
      I0 => rng_reg(24),
      I1 => rng_reg(23),
      I2 => rng_reg(22),
      I3 => rng_reg(27),
      I4 => rng_reg(26),
      I5 => rng_reg(25),
      O => \i__carry_i_53_n_0\
    );
\i__carry_i_54\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF9696FF96FFFF96"
    )
        port map (
      I0 => rng_reg(24),
      I1 => rng_reg(23),
      I2 => rng_reg(22),
      I3 => rng_reg(27),
      I4 => rng_reg(26),
      I5 => rng_reg(25),
      O => \i__carry_i_54_n_0\
    );
\i__carry_i_55\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => rng_reg(34),
      I1 => rng_reg(35),
      I2 => rng_reg(36),
      O => \i__carry_i_55_n_0\
    );
\i__carry_i_56\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rng_reg(31),
      I1 => rng_reg(32),
      I2 => rng_reg(33),
      O => \i__carry_i_56_n_0\
    );
\i__carry_i_57\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF969600"
    )
        port map (
      I0 => rng_reg(49),
      I1 => rng_reg(51),
      I2 => rng_reg(50),
      I3 => \i__carry_i_42_n_0\,
      I4 => \i__carry_i_43_n_0\,
      O => \i__carry_i_57_n_0\
    );
\i__carry_i_58\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"66696999"
    )
        port map (
      I0 => \i__carry_i_69_n_0\,
      I1 => \i__carry_i_68_n_0\,
      I2 => rng_reg(57),
      I3 => rng_reg(55),
      I4 => rng_reg(56),
      O => \i__carry_i_58_n_0\
    );
\i__carry_i_59\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2882AAAA"
    )
        port map (
      I0 => \i__carry_i_72_n_0\,
      I1 => rng_reg(9),
      I2 => rng_reg(8),
      I3 => rng_reg(7),
      I4 => \i__carry_i_73_n_0\,
      O => \i__carry_i_59_n_0\
    );
\i__carry_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2BB2B22B"
    )
        port map (
      I0 => \i__carry_i_14_n_0\,
      I1 => \i__carry_i_13_n_0\,
      I2 => \i__carry_i_10_n_0\,
      I3 => \i__carry_i_11_n_0\,
      I4 => \i__carry_i_12_n_0\,
      O => \i__carry_i_6_n_0\
    );
\i__carry_i_60\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6900FFFF"
    )
        port map (
      I0 => rng_reg(21),
      I1 => rng_reg(19),
      I2 => rng_reg(20),
      I3 => \i__carry_i_74_n_0\,
      I4 => \i__carry_i_75_n_0\,
      O => \i__carry_i_60_n_0\
    );
\i__carry_i_61\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(42),
      I1 => rng_reg(41),
      I2 => rng_reg(40),
      O => \i__carry_i_61_n_0\
    );
\i__carry_i_62\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(38),
      I1 => rng_reg(37),
      I2 => rng_reg(39),
      O => \i__carry_i_62_n_0\
    );
\i__carry_i_63\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(50),
      I1 => rng_reg(51),
      I2 => rng_reg(49),
      O => \i__carry_i_63_n_0\
    );
\i__carry_i_64\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => rng_reg(48),
      I1 => rng_reg(47),
      I2 => rng_reg(46),
      O => \i__carry_i_64_n_0\
    );
\i__carry_i_65\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"171717E817E8E8E8"
    )
        port map (
      I0 => rng_reg(33),
      I1 => rng_reg(32),
      I2 => rng_reg(31),
      I3 => rng_reg(29),
      I4 => rng_reg(28),
      I5 => rng_reg(30),
      O => \i__carry_i_65_n_0\
    );
\i__carry_i_66\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => rng_reg(16),
      I1 => rng_reg(17),
      I2 => rng_reg(18),
      I3 => rng_reg(13),
      I4 => rng_reg(14),
      I5 => rng_reg(15),
      O => \i__carry_i_66_n_0\
    );
\i__carry_i_67\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9669699669969669"
    )
        port map (
      I0 => rng_reg(4),
      I1 => rng_reg(5),
      I2 => rng_reg(6),
      I3 => rng_reg(10),
      I4 => rng_reg(11),
      I5 => rng_reg(12),
      O => \i__carry_i_67_n_0\
    );
\i__carry_i_68\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(60),
      I1 => rng_reg(58),
      I2 => rng_reg(59),
      O => \i__carry_i_68_n_0\
    );
\i__carry_i_69\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"17"
    )
        port map (
      I0 => rng_reg(63),
      I1 => rng_reg(61),
      I2 => rng_reg(62),
      O => \i__carry_i_69_n_0\
    );
\i__carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9669"
    )
        port map (
      I0 => \i__carry_i_19_n_0\,
      I1 => \i__carry_i_20_n_0\,
      I2 => \i__carry_i_21_n_0\,
      I3 => \i__carry_i_22_n_0\,
      O => \i__carry_i_7_n_0\
    );
\i__carry_i_70\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"69"
    )
        port map (
      I0 => rng_reg(49),
      I1 => rng_reg(51),
      I2 => rng_reg(50),
      O => \i__carry_i_70_n_0\
    );
\i__carry_i_71\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"96"
    )
        port map (
      I0 => rng_reg(60),
      I1 => rng_reg(58),
      I2 => rng_reg(59),
      O => \i__carry_i_71_n_0\
    );
\i__carry_i_72\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69FFFF69FF6969FF"
    )
        port map (
      I0 => rng_reg(12),
      I1 => rng_reg(11),
      I2 => rng_reg(10),
      I3 => rng_reg(6),
      I4 => rng_reg(5),
      I5 => rng_reg(4),
      O => \i__carry_i_72_n_0\
    );
\i__carry_i_73\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF9696FF96FFFF96"
    )
        port map (
      I0 => rng_reg(12),
      I1 => rng_reg(11),
      I2 => rng_reg(10),
      I3 => rng_reg(6),
      I4 => rng_reg(5),
      I5 => rng_reg(4),
      O => \i__carry_i_73_n_0\
    );
\i__carry_i_74\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"69FFFF69FF6969FF"
    )
        port map (
      I0 => rng_reg(15),
      I1 => rng_reg(14),
      I2 => rng_reg(13),
      I3 => rng_reg(18),
      I4 => rng_reg(17),
      I5 => rng_reg(16),
      O => \i__carry_i_74_n_0\
    );
\i__carry_i_75\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF9696FF96FFFF96"
    )
        port map (
      I0 => rng_reg(15),
      I1 => rng_reg(14),
      I2 => rng_reg(13),
      I3 => rng_reg(18),
      I4 => rng_reg(17),
      I5 => rng_reg(16),
      O => \i__carry_i_75_n_0\
    );
\i__carry_i_8\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"87E11E871E87781E"
    )
        port map (
      I0 => \i__carry_i_21_n_0\,
      I1 => \i__carry_i_22_n_0\,
      I2 => \i__carry_i_23_n_0\,
      I3 => \i__carry_i_24_n_0\,
      I4 => \i__carry_i_25_n_0\,
      I5 => \i__carry_i_26_n_0\,
      O => \i__carry_i_8_n_0\
    );
\i__carry_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0096"
    )
        port map (
      I0 => \i__carry_i_22_n_0\,
      I1 => \i__carry_i_21_n_0\,
      I2 => \i__carry_i_20_n_0\,
      I3 => \i__carry_i_19_n_0\,
      O => \i__carry_i_9_n_0\
    );
\num_of_1s0_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \num_of_1s0_inferred__0/i__carry_n_0\,
      CO(2) => \num_of_1s0_inferred__0/i__carry_n_1\,
      CO(1) => \num_of_1s0_inferred__0/i__carry_n_2\,
      CO(0) => \num_of_1s0_inferred__0/i__carry_n_3\,
      CYINIT => '0',
      DI(3) => \num_of_1s_reg_n_0_[3]\,
      DI(2) => \num_of_1s_reg_n_0_[2]\,
      DI(1) => \num_of_1s_reg_n_0_[1]\,
      DI(0) => \num_of_1s_reg_n_0_[0]\,
      O(3 downto 0) => p_0_in(3 downto 0),
      S(3) => \i__carry_i_1_n_0\,
      S(2) => \i__carry_i_2_n_0\,
      S(1) => \i__carry_i_3_n_0\,
      S(0) => \i__carry_i_4_n_0\
    );
\num_of_1s0_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \num_of_1s0_inferred__0/i__carry_n_0\,
      CO(3) => \num_of_1s0_inferred__0/i__carry__0_n_0\,
      CO(2) => \num_of_1s0_inferred__0/i__carry__0_n_1\,
      CO(1) => \num_of_1s0_inferred__0/i__carry__0_n_2\,
      CO(0) => \num_of_1s0_inferred__0/i__carry__0_n_3\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \num_of_1s_reg_n_0_[6]\,
      DI(1) => \num_of_1s_reg_n_0_[5]\,
      DI(0) => \num_of_1s_reg_n_0_[4]\,
      O(3 downto 0) => p_0_in(7 downto 4),
      S(3) => \num_of_1s_reg_n_0_[7]\,
      S(2) => \i__carry__0_i_1_n_0\,
      S(1) => \i__carry__0_i_2_n_0\,
      S(0) => \i__carry__0_i_3_n_0\
    );
\num_of_1s0_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \num_of_1s0_inferred__0/i__carry__0_n_0\,
      CO(3) => \num_of_1s0_inferred__0/i__carry__1_n_0\,
      CO(2) => \num_of_1s0_inferred__0/i__carry__1_n_1\,
      CO(1) => \num_of_1s0_inferred__0/i__carry__1_n_2\,
      CO(0) => \num_of_1s0_inferred__0/i__carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => p_0_in(11 downto 8),
      S(3) => \num_of_1s_reg_n_0_[11]\,
      S(2) => \num_of_1s_reg_n_0_[10]\,
      S(1) => \num_of_1s_reg_n_0_[9]\,
      S(0) => \num_of_1s_reg_n_0_[8]\
    );
\num_of_1s0_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \num_of_1s0_inferred__0/i__carry__1_n_0\,
      CO(3) => \num_of_1s0_inferred__0/i__carry__2_n_0\,
      CO(2) => \num_of_1s0_inferred__0/i__carry__2_n_1\,
      CO(1) => \num_of_1s0_inferred__0/i__carry__2_n_2\,
      CO(0) => \num_of_1s0_inferred__0/i__carry__2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => p_0_in(15 downto 12),
      S(3) => \num_of_1s_reg_n_0_[15]\,
      S(2) => \num_of_1s_reg_n_0_[14]\,
      S(1) => \num_of_1s_reg_n_0_[13]\,
      S(0) => \num_of_1s_reg_n_0_[12]\
    );
\num_of_1s0_inferred__0/i__carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \num_of_1s0_inferred__0/i__carry__2_n_0\,
      CO(3) => \NLW_num_of_1s0_inferred__0/i__carry__3_CO_UNCONNECTED\(3),
      CO(2) => \num_of_1s0_inferred__0/i__carry__3_n_1\,
      CO(1) => \num_of_1s0_inferred__0/i__carry__3_n_2\,
      CO(0) => \num_of_1s0_inferred__0/i__carry__3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => p_0_in(19 downto 16),
      S(3) => \num_of_1s_reg_n_0_[19]\,
      S(2) => \num_of_1s_reg_n_0_[18]\,
      S(1) => \num_of_1s_reg_n_0_[17]\,
      S(0) => \num_of_1s_reg_n_0_[16]\
    );
\num_of_1s[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => Q(0),
      I1 => Q(2),
      I2 => Q(1),
      I3 => Q(4),
      I4 => Q(3),
      O => stat_trng_rst
    );
\num_of_1s[19]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rng_ready_d0,
      I1 => rng_ready_d1,
      O => \^e\(0)
    );
\num_of_1s_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(0),
      Q => \num_of_1s_reg_n_0_[0]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(10),
      Q => \num_of_1s_reg_n_0_[10]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(11),
      Q => \num_of_1s_reg_n_0_[11]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(12),
      Q => \num_of_1s_reg_n_0_[12]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(13),
      Q => \num_of_1s_reg_n_0_[13]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(14),
      Q => \num_of_1s_reg_n_0_[14]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(15),
      Q => \num_of_1s_reg_n_0_[15]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(16),
      Q => \num_of_1s_reg_n_0_[16]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(17),
      Q => \num_of_1s_reg_n_0_[17]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(18),
      Q => \num_of_1s_reg_n_0_[18]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(19),
      Q => \num_of_1s_reg_n_0_[19]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(1),
      Q => \num_of_1s_reg_n_0_[1]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(2),
      Q => \num_of_1s_reg_n_0_[2]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(3),
      Q => \num_of_1s_reg_n_0_[3]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(4),
      Q => \num_of_1s_reg_n_0_[4]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(5),
      Q => \num_of_1s_reg_n_0_[5]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(6),
      Q => \num_of_1s_reg_n_0_[6]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(7),
      Q => \num_of_1s_reg_n_0_[7]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(8),
      Q => \num_of_1s_reg_n_0_[8]\,
      R => stat_trng_rst
    );
\num_of_1s_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \^e\(0),
      D => p_0_in(9),
      Q => \num_of_1s_reg_n_0_[9]\,
      R => stat_trng_rst
    );
rng_ready_d0_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => rng_ready,
      Q => rng_ready_d0,
      R => '0'
    );
rng_ready_d1_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => rng_ready_d0,
      Q => rng_ready_d1,
      R => '0'
    );
\rng_word_counter[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => rng_ready_d1,
      I1 => rng_ready_d0,
      I2 => stat_done,
      O => rng_word_counter0
    );
\rng_word_counter[0]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000100"
    )
        port map (
      I0 => \rng_word_counter[0]_i_5_n_0\,
      I1 => rng_word_counter_reg(15),
      I2 => rng_word_counter_reg(19),
      I3 => rng_word_counter_reg(10),
      I4 => rng_word_counter_reg(1),
      I5 => \rng_word_counter[0]_i_6_n_0\,
      O => stat_done
    );
\rng_word_counter[0]_i_4\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => rng_word_counter_reg(0),
      O => \rng_word_counter[0]_i_4_n_0\
    );
\rng_word_counter[0]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => rng_word_counter_reg(11),
      I1 => rng_word_counter_reg(17),
      I2 => rng_word_counter_reg(0),
      I3 => rng_word_counter_reg(6),
      O => \rng_word_counter[0]_i_5_n_0\
    );
\rng_word_counter[0]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => rng_word_counter_reg(7),
      I1 => rng_word_counter_reg(16),
      I2 => rng_word_counter_reg(2),
      I3 => rng_word_counter_reg(5),
      I4 => \rng_word_counter[0]_i_7_n_0\,
      I5 => \rng_word_counter[0]_i_8_n_0\,
      O => \rng_word_counter[0]_i_6_n_0\
    );
\rng_word_counter[0]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFDF"
    )
        port map (
      I0 => rng_word_counter_reg(13),
      I1 => rng_word_counter_reg(18),
      I2 => rng_word_counter_reg(3),
      I3 => rng_word_counter_reg(14),
      O => \rng_word_counter[0]_i_7_n_0\
    );
\rng_word_counter[0]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rng_word_counter_reg(12),
      I1 => rng_word_counter_reg(8),
      I2 => rng_word_counter_reg(9),
      I3 => rng_word_counter_reg(4),
      O => \rng_word_counter[0]_i_8_n_0\
    );
\rng_word_counter_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[0]_i_2_n_7\,
      Q => rng_word_counter_reg(0),
      R => stat_trng_rst
    );
\rng_word_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \rng_word_counter_reg[0]_i_2_n_0\,
      CO(2) => \rng_word_counter_reg[0]_i_2_n_1\,
      CO(1) => \rng_word_counter_reg[0]_i_2_n_2\,
      CO(0) => \rng_word_counter_reg[0]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \rng_word_counter_reg[0]_i_2_n_4\,
      O(2) => \rng_word_counter_reg[0]_i_2_n_5\,
      O(1) => \rng_word_counter_reg[0]_i_2_n_6\,
      O(0) => \rng_word_counter_reg[0]_i_2_n_7\,
      S(3 downto 1) => rng_word_counter_reg(3 downto 1),
      S(0) => \rng_word_counter[0]_i_4_n_0\
    );
\rng_word_counter_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[8]_i_1_n_5\,
      Q => rng_word_counter_reg(10),
      R => stat_trng_rst
    );
\rng_word_counter_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[8]_i_1_n_4\,
      Q => rng_word_counter_reg(11),
      R => stat_trng_rst
    );
\rng_word_counter_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[12]_i_1_n_7\,
      Q => rng_word_counter_reg(12),
      R => stat_trng_rst
    );
\rng_word_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rng_word_counter_reg[8]_i_1_n_0\,
      CO(3) => \rng_word_counter_reg[12]_i_1_n_0\,
      CO(2) => \rng_word_counter_reg[12]_i_1_n_1\,
      CO(1) => \rng_word_counter_reg[12]_i_1_n_2\,
      CO(0) => \rng_word_counter_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rng_word_counter_reg[12]_i_1_n_4\,
      O(2) => \rng_word_counter_reg[12]_i_1_n_5\,
      O(1) => \rng_word_counter_reg[12]_i_1_n_6\,
      O(0) => \rng_word_counter_reg[12]_i_1_n_7\,
      S(3 downto 0) => rng_word_counter_reg(15 downto 12)
    );
\rng_word_counter_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[12]_i_1_n_6\,
      Q => rng_word_counter_reg(13),
      R => stat_trng_rst
    );
\rng_word_counter_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[12]_i_1_n_5\,
      Q => rng_word_counter_reg(14),
      R => stat_trng_rst
    );
\rng_word_counter_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[12]_i_1_n_4\,
      Q => rng_word_counter_reg(15),
      R => stat_trng_rst
    );
\rng_word_counter_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[16]_i_1_n_7\,
      Q => rng_word_counter_reg(16),
      R => stat_trng_rst
    );
\rng_word_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rng_word_counter_reg[12]_i_1_n_0\,
      CO(3) => \NLW_rng_word_counter_reg[16]_i_1_CO_UNCONNECTED\(3),
      CO(2) => \rng_word_counter_reg[16]_i_1_n_1\,
      CO(1) => \rng_word_counter_reg[16]_i_1_n_2\,
      CO(0) => \rng_word_counter_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rng_word_counter_reg[16]_i_1_n_4\,
      O(2) => \rng_word_counter_reg[16]_i_1_n_5\,
      O(1) => \rng_word_counter_reg[16]_i_1_n_6\,
      O(0) => \rng_word_counter_reg[16]_i_1_n_7\,
      S(3 downto 0) => rng_word_counter_reg(19 downto 16)
    );
\rng_word_counter_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[16]_i_1_n_6\,
      Q => rng_word_counter_reg(17),
      R => stat_trng_rst
    );
\rng_word_counter_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[16]_i_1_n_5\,
      Q => rng_word_counter_reg(18),
      R => stat_trng_rst
    );
\rng_word_counter_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[16]_i_1_n_4\,
      Q => rng_word_counter_reg(19),
      R => stat_trng_rst
    );
\rng_word_counter_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[0]_i_2_n_6\,
      Q => rng_word_counter_reg(1),
      R => stat_trng_rst
    );
\rng_word_counter_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[0]_i_2_n_5\,
      Q => rng_word_counter_reg(2),
      R => stat_trng_rst
    );
\rng_word_counter_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[0]_i_2_n_4\,
      Q => rng_word_counter_reg(3),
      R => stat_trng_rst
    );
\rng_word_counter_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[4]_i_1_n_7\,
      Q => rng_word_counter_reg(4),
      R => stat_trng_rst
    );
\rng_word_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rng_word_counter_reg[0]_i_2_n_0\,
      CO(3) => \rng_word_counter_reg[4]_i_1_n_0\,
      CO(2) => \rng_word_counter_reg[4]_i_1_n_1\,
      CO(1) => \rng_word_counter_reg[4]_i_1_n_2\,
      CO(0) => \rng_word_counter_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rng_word_counter_reg[4]_i_1_n_4\,
      O(2) => \rng_word_counter_reg[4]_i_1_n_5\,
      O(1) => \rng_word_counter_reg[4]_i_1_n_6\,
      O(0) => \rng_word_counter_reg[4]_i_1_n_7\,
      S(3 downto 0) => rng_word_counter_reg(7 downto 4)
    );
\rng_word_counter_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[4]_i_1_n_6\,
      Q => rng_word_counter_reg(5),
      R => stat_trng_rst
    );
\rng_word_counter_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[4]_i_1_n_5\,
      Q => rng_word_counter_reg(6),
      R => stat_trng_rst
    );
\rng_word_counter_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[4]_i_1_n_4\,
      Q => rng_word_counter_reg(7),
      R => stat_trng_rst
    );
\rng_word_counter_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[8]_i_1_n_7\,
      Q => rng_word_counter_reg(8),
      R => stat_trng_rst
    );
\rng_word_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \rng_word_counter_reg[4]_i_1_n_0\,
      CO(3) => \rng_word_counter_reg[8]_i_1_n_0\,
      CO(2) => \rng_word_counter_reg[8]_i_1_n_1\,
      CO(1) => \rng_word_counter_reg[8]_i_1_n_2\,
      CO(0) => \rng_word_counter_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \rng_word_counter_reg[8]_i_1_n_4\,
      O(2) => \rng_word_counter_reg[8]_i_1_n_5\,
      O(1) => \rng_word_counter_reg[8]_i_1_n_6\,
      O(0) => \rng_word_counter_reg[8]_i_1_n_7\,
      S(3 downto 0) => rng_word_counter_reg(11 downto 8)
    );
\rng_word_counter_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => rng_word_counter0,
      D => \rng_word_counter_reg[8]_i_1_n_6\,
      Q => rng_word_counter_reg(9),
      R => stat_trng_rst
    );
stat_error_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFAACFAA"
    )
        port map (
      I0 => \^stat_error\,
      I1 => stat_error_i_2_n_0,
      I2 => stat_error_i_3_n_0,
      I3 => stat_done,
      I4 => stat_error_i_4_n_0,
      O => stat_error_i_1_n_0
    );
stat_error_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8AAAAA8A8A8A8"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[13]\,
      I1 => \num_of_1s_reg_n_0_[11]\,
      I2 => \num_of_1s_reg_n_0_[12]\,
      I3 => stat_error_i_5_n_0,
      I4 => stat_error_i_6_n_0,
      I5 => \num_of_1s_reg_n_0_[10]\,
      O => stat_error_i_2_n_0
    );
stat_error_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BAAAAAAAAAAAAAAA"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[13]\,
      I1 => stat_error_i_6_n_0,
      I2 => \num_of_1s_reg_n_0_[11]\,
      I3 => \num_of_1s_reg_n_0_[10]\,
      I4 => \num_of_1s_reg_n_0_[12]\,
      I5 => stat_error_i_7_n_0,
      O => stat_error_i_3_n_0
    );
stat_error_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FDFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[18]\,
      I1 => \num_of_1s_reg_n_0_[14]\,
      I2 => \num_of_1s_reg_n_0_[19]\,
      I3 => \num_of_1s_reg_n_0_[16]\,
      I4 => \num_of_1s_reg_n_0_[15]\,
      I5 => \num_of_1s_reg_n_0_[17]\,
      O => stat_error_i_4_n_0
    );
stat_error_i_5: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[8]\,
      I1 => \num_of_1s_reg_n_0_[5]\,
      I2 => \num_of_1s_reg_n_0_[3]\,
      O => stat_error_i_5_n_0
    );
stat_error_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"11111113"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[8]\,
      I1 => \num_of_1s_reg_n_0_[9]\,
      I2 => \num_of_1s_reg_n_0_[7]\,
      I3 => \num_of_1s_reg_n_0_[6]\,
      I4 => \num_of_1s_reg_n_0_[4]\,
      O => stat_error_i_6_n_0
    );
stat_error_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAEAEAEAEAEAEAAA"
    )
        port map (
      I0 => stat_error_i_8_n_0,
      I1 => \num_of_1s_reg_n_0_[3]\,
      I2 => \num_of_1s_reg_n_0_[5]\,
      I3 => \num_of_1s_reg_n_0_[1]\,
      I4 => \num_of_1s_reg_n_0_[0]\,
      I5 => \num_of_1s_reg_n_0_[2]\,
      O => stat_error_i_7_n_0
    );
stat_error_i_8: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \num_of_1s_reg_n_0_[9]\,
      I1 => \num_of_1s_reg_n_0_[7]\,
      I2 => \num_of_1s_reg_n_0_[6]\,
      O => stat_error_i_8_n_0
    );
stat_error_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => stat_error_i_1_n_0,
      Q => \^stat_error\,
      R => '0'
    );
end STRUCTURE;
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`protect begin_protected
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
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`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO is
  port (
    en : in STD_LOGIC;
    rng_reg : out STD_LOGIC_VECTOR ( 63 downto 0 );
    rng_ready : out STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO : entity is "TRNG_RO";
  attribute keep_hierarchy : string;
  attribute keep_hierarchy of cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO : entity is "true";
end cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO is
  signal \bit_counter[2]_i_1_n_0\ : STD_LOGIC;
  signal bit_counter_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal clear : STD_LOGIC;
  signal clk : STD_LOGIC;
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^rng_reg\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal ro_bit_out : STD_LOGIC;
  signal ro_sample_clk : STD_LOGIC;
  signal ro_sample_clk_div16 : STD_LOGIC;
  signal ro_sample_clk_div16_i_1_n_0 : STD_LOGIC;
  signal ro_sample_clk_div2 : STD_LOGIC;
  signal ro_sample_clk_div2_i_1_n_0 : STD_LOGIC;
  signal ro_sample_clk_div32_i_1_n_0 : STD_LOGIC;
  signal ro_sample_clk_div4 : STD_LOGIC;
  signal ro_sample_clk_div4_i_1_n_0 : STD_LOGIC;
  signal ro_sample_clk_div8 : STD_LOGIC;
  signal ro_sample_clk_div8_i_1_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \bit_counter[1]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \bit_counter[2]_i_1\ : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of \bit_counter[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \bit_counter[4]_i_1\ : label is "soft_lutpair0";
  attribute KEEP_HIERARCHY of ro_0 : label is "true";
  attribute KEEP_HIERARCHY of ro_sample : label is "true";
begin
  rng_reg(63 downto 0) <= \^rng_reg\(63 downto 0);
\bit_counter[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => bit_counter_reg(0),
      O => p_0_in(0)
    );
\bit_counter[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => bit_counter_reg(0),
      I1 => bit_counter_reg(1),
      O => p_0_in(1)
    );
\bit_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"78"
    )
        port map (
      I0 => bit_counter_reg(1),
      I1 => bit_counter_reg(0),
      I2 => bit_counter_reg(2),
      O => \bit_counter[2]_i_1_n_0\
    );
\bit_counter[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F80"
    )
        port map (
      I0 => bit_counter_reg(1),
      I1 => bit_counter_reg(0),
      I2 => bit_counter_reg(2),
      I3 => bit_counter_reg(3),
      O => p_0_in(3)
    );
\bit_counter[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF8000"
    )
        port map (
      I0 => bit_counter_reg(2),
      I1 => bit_counter_reg(0),
      I2 => bit_counter_reg(1),
      I3 => bit_counter_reg(3),
      I4 => bit_counter_reg(4),
      O => p_0_in(4)
    );
\bit_counter[5]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => en,
      O => clear
    );
\bit_counter[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFF80000000"
    )
        port map (
      I0 => bit_counter_reg(3),
      I1 => bit_counter_reg(1),
      I2 => bit_counter_reg(0),
      I3 => bit_counter_reg(2),
      I4 => bit_counter_reg(4),
      I5 => bit_counter_reg(5),
      O => p_0_in(5)
    );
\bit_counter_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => p_0_in(0),
      Q => bit_counter_reg(0),
      R => clear
    );
\bit_counter_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => p_0_in(1),
      Q => bit_counter_reg(1),
      R => clear
    );
\bit_counter_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \bit_counter[2]_i_1_n_0\,
      Q => bit_counter_reg(2),
      R => clear
    );
\bit_counter_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => p_0_in(3),
      Q => bit_counter_reg(3),
      R => clear
    );
\bit_counter_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => p_0_in(4),
      Q => bit_counter_reg(4),
      R => clear
    );
\bit_counter_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => p_0_in(5),
      Q => bit_counter_reg(5),
      R => clear
    );
rng_ready_INST_0: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => bit_counter_reg(3),
      I1 => bit_counter_reg(5),
      I2 => bit_counter_reg(4),
      I3 => bit_counter_reg(2),
      I4 => bit_counter_reg(0),
      I5 => bit_counter_reg(1),
      O => rng_ready
    );
\rng_reg_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => ro_bit_out,
      Q => \^rng_reg\(0),
      R => '0'
    );
\rng_reg_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(9),
      Q => \^rng_reg\(10),
      R => '0'
    );
\rng_reg_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(10),
      Q => \^rng_reg\(11),
      R => '0'
    );
\rng_reg_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(11),
      Q => \^rng_reg\(12),
      R => '0'
    );
\rng_reg_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(12),
      Q => \^rng_reg\(13),
      R => '0'
    );
\rng_reg_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(13),
      Q => \^rng_reg\(14),
      R => '0'
    );
\rng_reg_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(14),
      Q => \^rng_reg\(15),
      R => '0'
    );
\rng_reg_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(15),
      Q => \^rng_reg\(16),
      R => '0'
    );
\rng_reg_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(16),
      Q => \^rng_reg\(17),
      R => '0'
    );
\rng_reg_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(17),
      Q => \^rng_reg\(18),
      R => '0'
    );
\rng_reg_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(18),
      Q => \^rng_reg\(19),
      R => '0'
    );
\rng_reg_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(0),
      Q => \^rng_reg\(1),
      R => '0'
    );
\rng_reg_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(19),
      Q => \^rng_reg\(20),
      R => '0'
    );
\rng_reg_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(20),
      Q => \^rng_reg\(21),
      R => '0'
    );
\rng_reg_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(21),
      Q => \^rng_reg\(22),
      R => '0'
    );
\rng_reg_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(22),
      Q => \^rng_reg\(23),
      R => '0'
    );
\rng_reg_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(23),
      Q => \^rng_reg\(24),
      R => '0'
    );
\rng_reg_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(24),
      Q => \^rng_reg\(25),
      R => '0'
    );
\rng_reg_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(25),
      Q => \^rng_reg\(26),
      R => '0'
    );
\rng_reg_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(26),
      Q => \^rng_reg\(27),
      R => '0'
    );
\rng_reg_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(27),
      Q => \^rng_reg\(28),
      R => '0'
    );
\rng_reg_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(28),
      Q => \^rng_reg\(29),
      R => '0'
    );
\rng_reg_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(1),
      Q => \^rng_reg\(2),
      R => '0'
    );
\rng_reg_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(29),
      Q => \^rng_reg\(30),
      R => '0'
    );
\rng_reg_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(30),
      Q => \^rng_reg\(31),
      R => '0'
    );
\rng_reg_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(31),
      Q => \^rng_reg\(32),
      R => '0'
    );
\rng_reg_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(32),
      Q => \^rng_reg\(33),
      R => '0'
    );
\rng_reg_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(33),
      Q => \^rng_reg\(34),
      R => '0'
    );
\rng_reg_reg[35]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(34),
      Q => \^rng_reg\(35),
      R => '0'
    );
\rng_reg_reg[36]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(35),
      Q => \^rng_reg\(36),
      R => '0'
    );
\rng_reg_reg[37]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(36),
      Q => \^rng_reg\(37),
      R => '0'
    );
\rng_reg_reg[38]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(37),
      Q => \^rng_reg\(38),
      R => '0'
    );
\rng_reg_reg[39]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(38),
      Q => \^rng_reg\(39),
      R => '0'
    );
\rng_reg_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(2),
      Q => \^rng_reg\(3),
      R => '0'
    );
\rng_reg_reg[40]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(39),
      Q => \^rng_reg\(40),
      R => '0'
    );
\rng_reg_reg[41]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(40),
      Q => \^rng_reg\(41),
      R => '0'
    );
\rng_reg_reg[42]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(41),
      Q => \^rng_reg\(42),
      R => '0'
    );
\rng_reg_reg[43]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(42),
      Q => \^rng_reg\(43),
      R => '0'
    );
\rng_reg_reg[44]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(43),
      Q => \^rng_reg\(44),
      R => '0'
    );
\rng_reg_reg[45]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(44),
      Q => \^rng_reg\(45),
      R => '0'
    );
\rng_reg_reg[46]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(45),
      Q => \^rng_reg\(46),
      R => '0'
    );
\rng_reg_reg[47]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(46),
      Q => \^rng_reg\(47),
      R => '0'
    );
\rng_reg_reg[48]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(47),
      Q => \^rng_reg\(48),
      R => '0'
    );
\rng_reg_reg[49]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(48),
      Q => \^rng_reg\(49),
      R => '0'
    );
\rng_reg_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(3),
      Q => \^rng_reg\(4),
      R => '0'
    );
\rng_reg_reg[50]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(49),
      Q => \^rng_reg\(50),
      R => '0'
    );
\rng_reg_reg[51]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(50),
      Q => \^rng_reg\(51),
      R => '0'
    );
\rng_reg_reg[52]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(51),
      Q => \^rng_reg\(52),
      R => '0'
    );
\rng_reg_reg[53]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(52),
      Q => \^rng_reg\(53),
      R => '0'
    );
\rng_reg_reg[54]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(53),
      Q => \^rng_reg\(54),
      R => '0'
    );
\rng_reg_reg[55]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(54),
      Q => \^rng_reg\(55),
      R => '0'
    );
\rng_reg_reg[56]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(55),
      Q => \^rng_reg\(56),
      R => '0'
    );
\rng_reg_reg[57]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(56),
      Q => \^rng_reg\(57),
      R => '0'
    );
\rng_reg_reg[58]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(57),
      Q => \^rng_reg\(58),
      R => '0'
    );
\rng_reg_reg[59]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(58),
      Q => \^rng_reg\(59),
      R => '0'
    );
\rng_reg_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(4),
      Q => \^rng_reg\(5),
      R => '0'
    );
\rng_reg_reg[60]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(59),
      Q => \^rng_reg\(60),
      R => '0'
    );
\rng_reg_reg[61]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(60),
      Q => \^rng_reg\(61),
      R => '0'
    );
\rng_reg_reg[62]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(61),
      Q => \^rng_reg\(62),
      R => '0'
    );
\rng_reg_reg[63]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(62),
      Q => \^rng_reg\(63),
      R => '0'
    );
\rng_reg_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(5),
      Q => \^rng_reg\(6),
      R => '0'
    );
\rng_reg_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(6),
      Q => \^rng_reg\(7),
      R => '0'
    );
\rng_reg_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(7),
      Q => \^rng_reg\(8),
      R => '0'
    );
\rng_reg_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \^rng_reg\(8),
      Q => \^rng_reg\(9),
      R => '0'
    );
ro_0: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv
     port map (
      bit_out => ro_bit_out,
      en => en
    );
ro_sample: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv
     port map (
      bit_out => ro_sample_clk,
      en => en
    );
ro_sample_clk_div16_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ro_sample_clk_div16,
      O => ro_sample_clk_div16_i_1_n_0
    );
ro_sample_clk_div16_reg: unisim.vcomponents.FDRE
     port map (
      C => ro_sample_clk_div8,
      CE => '1',
      D => ro_sample_clk_div16_i_1_n_0,
      Q => ro_sample_clk_div16,
      R => '0'
    );
ro_sample_clk_div2_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ro_sample_clk_div2,
      O => ro_sample_clk_div2_i_1_n_0
    );
ro_sample_clk_div2_reg: unisim.vcomponents.FDRE
     port map (
      C => ro_sample_clk,
      CE => '1',
      D => ro_sample_clk_div2_i_1_n_0,
      Q => ro_sample_clk_div2,
      R => '0'
    );
ro_sample_clk_div32_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => clk,
      O => ro_sample_clk_div32_i_1_n_0
    );
ro_sample_clk_div32_reg: unisim.vcomponents.FDRE
     port map (
      C => ro_sample_clk_div16,
      CE => '1',
      D => ro_sample_clk_div32_i_1_n_0,
      Q => clk,
      R => '0'
    );
ro_sample_clk_div4_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ro_sample_clk_div4,
      O => ro_sample_clk_div4_i_1_n_0
    );
ro_sample_clk_div4_reg: unisim.vcomponents.FDRE
     port map (
      C => ro_sample_clk_div2,
      CE => '1',
      D => ro_sample_clk_div4_i_1_n_0,
      Q => ro_sample_clk_div4,
      R => '0'
    );
ro_sample_clk_div8_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => ro_sample_clk_div8,
      O => ro_sample_clk_div8_i_1_n_0
    );
ro_sample_clk_div8_reg: unisim.vcomponents.FDRE
     port map (
      C => ro_sample_clk_div4,
      CE => '1',
      D => ro_sample_clk_div8_i_1_n_0,
      Q => ro_sample_clk_div8,
      R => '0'
    );
end STRUCTURE;
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 2368)
`protect data_block
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`protect end_protected
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`protect key_block
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`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`protect key_block
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`protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1120)
`protect data_block
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper is
  port (
    \command_reg0_reg[0]\ : out STD_LOGIC;
    dina : out STD_LOGIC_VECTOR ( 63 downto 0 );
    wea : out STD_LOGIC_VECTOR ( 0 to 0 );
    S : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \command_reg0_reg[28]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \command_reg0_reg[32]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    error_reg_0 : out STD_LOGIC;
    clk : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 24 downto 0 );
    \^d\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    dina_ext_high_word : in STD_LOGIC_VECTOR ( 26 downto 0 );
    control_low_word : in STD_LOGIC_VECTOR ( 11 downto 0 );
    error_trng_reg_reg : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper : entity is "TRNG_wrapper";
end cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper is
  signal BR_i_66_n_0 : STD_LOGIC;
  signal bitgen_done : STD_LOGIC;
  signal bitgen_done_carry_i_1_n_0 : STD_LOGIC;
  signal bitgen_done_carry_i_2_n_0 : STD_LOGIC;
  signal bitgen_done_carry_i_3_n_0 : STD_LOGIC;
  signal bitgen_done_carry_i_4_n_0 : STD_LOGIC;
  signal bitgen_done_carry_n_1 : STD_LOGIC;
  signal bitgen_done_carry_n_2 : STD_LOGIC;
  signal bitgen_done_carry_n_3 : STD_LOGIC;
  signal enable_TRO : STD_LOGIC;
  signal enable_TRO_for_bitgen : STD_LOGIC;
  signal enable_TRO_for_bitgen_i_1_n_0 : STD_LOGIC;
  signal error_trng : STD_LOGIC;
  signal rng_ready : STD_LOGIC;
  signal stat_error : STD_LOGIC;
  signal trng_out : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trng_rst : STD_LOGIC;
  signal trng_wea : STD_LOGIC;
  signal write_address1 : STD_LOGIC;
  signal \write_address1_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \write_address1_carry__0_i_2_n_0\ : STD_LOGIC;
  signal write_address1_carry_i_1_n_0 : STD_LOGIC;
  signal write_address1_carry_i_2_n_0 : STD_LOGIC;
  signal write_address1_carry_i_3_n_0 : STD_LOGIC;
  signal write_address1_carry_i_4_n_0 : STD_LOGIC;
  signal write_address1_carry_i_5_n_0 : STD_LOGIC;
  signal write_address1_carry_i_6_n_0 : STD_LOGIC;
  signal write_address1_carry_i_7_n_0 : STD_LOGIC;
  signal write_address1_carry_i_8_n_0 : STD_LOGIC;
  signal write_address1_carry_n_0 : STD_LOGIC;
  signal write_address1_carry_n_1 : STD_LOGIC;
  signal write_address1_carry_n_2 : STD_LOGIC;
  signal write_address1_carry_n_3 : STD_LOGIC;
  signal \write_address[0]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[1]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[2]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[3]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[3]_i_2_n_0\ : STD_LOGIC;
  signal \write_address[4]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[5]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[6]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[7]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[7]_i_2_n_0\ : STD_LOGIC;
  signal \write_address[8]_i_1_n_0\ : STD_LOGIC;
  signal \write_address[8]_i_2_n_0\ : STD_LOGIC;
  signal \write_address[9]_i_1_n_0\ : STD_LOGIC;
  signal write_address_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal write_rng_data0 : STD_LOGIC;
  signal NLW_bitgen_done_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_write_address1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_write_address1_carry__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_write_address1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute KEEP_HIERARCHY : string;
  attribute KEEP_HIERARCHY of TRO : label is "true";
  attribute COMPARATOR_THRESHOLD : integer;
  attribute COMPARATOR_THRESHOLD of write_address1_carry : label is 11;
  attribute COMPARATOR_THRESHOLD of \write_address1_carry__0\ : label is 11;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \write_address[0]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \write_address[1]_i_1\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \write_address[2]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \write_address[3]_i_2\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \write_address[5]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \write_address[6]_i_1\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \write_address[7]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \write_address[8]_i_2\ : label is "soft_lutpair31";
begin
BR_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88B8"
    )
        port map (
      I0 => trng_wea,
      I1 => BR_i_66_n_0,
      I2 => control_low_word(10),
      I3 => control_low_word(11),
      O => wea(0)
    );
BR_i_10: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(55),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(18),
      O => dina(55)
    );
BR_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(54),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(17),
      O => dina(54)
    );
BR_i_12: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(53),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(16),
      O => dina(53)
    );
BR_i_13: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(52),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(15),
      O => dina(52)
    );
BR_i_14: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(51),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(14),
      O => dina(51)
    );
BR_i_15: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(50),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(13),
      O => dina(50)
    );
BR_i_16: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(49),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(12),
      O => dina(49)
    );
BR_i_17: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(48),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(11),
      O => dina(48)
    );
BR_i_18: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(47),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(10),
      O => dina(47)
    );
BR_i_19: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(46),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(9),
      O => dina(46)
    );
BR_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(63),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(26),
      O => dina(63)
    );
BR_i_20: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(45),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(8),
      O => dina(45)
    );
BR_i_21: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(44),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(7),
      O => dina(44)
    );
BR_i_22: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(43),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(6),
      O => dina(43)
    );
BR_i_23: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(42),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(5),
      O => dina(42)
    );
BR_i_24: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(41),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(4),
      O => dina(41)
    );
BR_i_25: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(40),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(3),
      O => dina(40)
    );
BR_i_26: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(39),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(2),
      O => dina(39)
    );
BR_i_27: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(38),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(1),
      O => dina(38)
    );
BR_i_28: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(37),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(0),
      O => dina(37)
    );
BR_i_29: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(36),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(36),
      O => dina(36)
    );
BR_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(62),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(25),
      O => dina(62)
    );
BR_i_30: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(35),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(35),
      O => dina(35)
    );
BR_i_31: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(34),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(34),
      O => dina(34)
    );
BR_i_32: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(33),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(33),
      O => dina(33)
    );
BR_i_33: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(32),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(32),
      O => dina(32)
    );
BR_i_34: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(31),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(31),
      O => dina(31)
    );
BR_i_35: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(30),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(30),
      O => dina(30)
    );
BR_i_36: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(29),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(29),
      O => dina(29)
    );
BR_i_37: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(28),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(28),
      O => dina(28)
    );
BR_i_38: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(27),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(27),
      O => dina(27)
    );
BR_i_39: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(26),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(26),
      O => dina(26)
    );
BR_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(61),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(24),
      O => dina(61)
    );
BR_i_40: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(25),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(25),
      O => dina(25)
    );
BR_i_41: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(24),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(24),
      O => dina(24)
    );
BR_i_42: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(23),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(23),
      O => dina(23)
    );
BR_i_43: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(22),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(22),
      O => dina(22)
    );
BR_i_44: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(21),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(21),
      O => dina(21)
    );
BR_i_45: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(20),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(20),
      O => dina(20)
    );
BR_i_46: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(19),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(19),
      O => dina(19)
    );
BR_i_47: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(18),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(18),
      O => dina(18)
    );
BR_i_48: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(17),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(17),
      O => dina(17)
    );
BR_i_49: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(16),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(16),
      O => dina(16)
    );
BR_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(60),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(23),
      O => dina(60)
    );
BR_i_50: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(15),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(15),
      O => dina(15)
    );
BR_i_51: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(14),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(14),
      O => dina(14)
    );
BR_i_52: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(13),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(13),
      O => dina(13)
    );
BR_i_53: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(12),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(12),
      O => dina(12)
    );
BR_i_54: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(11),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(11),
      O => dina(11)
    );
BR_i_55: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(10),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(10),
      O => dina(10)
    );
BR_i_56: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(9),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(9),
      O => dina(9)
    );
BR_i_57: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(8),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(8),
      O => dina(8)
    );
BR_i_58: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(7),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(7),
      O => dina(7)
    );
BR_i_59: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(6),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(6),
      O => dina(6)
    );
BR_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(59),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(22),
      O => dina(59)
    );
BR_i_60: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(5),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(5),
      O => dina(5)
    );
BR_i_61: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(4),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(4),
      O => dina(4)
    );
BR_i_62: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(3),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(3),
      O => dina(3)
    );
BR_i_63: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(2),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(2),
      O => dina(2)
    );
BR_i_64: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(1),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(1),
      O => dina(1)
    );
BR_i_65: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(0),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => \^d\(0),
      O => dina(0)
    );
BR_i_66: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => Q(3),
      I1 => Q(4),
      I2 => Q(1),
      I3 => Q(2),
      O => BR_i_66_n_0
    );
BR_i_7: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(58),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(21),
      O => dina(58)
    );
BR_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(57),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(20),
      O => dina(57)
    );
BR_i_9: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFEFFF00002000"
    )
        port map (
      I0 => trng_out(56),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => dina_ext_high_word(19),
      O => dina(56)
    );
STest: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test
     port map (
      CO(0) => bitgen_done,
      D(0) => D(0),
      E(0) => write_rng_data0,
      Q(4 downto 0) => Q(4 downto 0),
      clk => clk,
      \command_reg0_reg[0]\ => \command_reg0_reg[0]\,
      en => enable_TRO,
      enable_TRO_for_bitgen => enable_TRO_for_bitgen,
      error_reg => error_reg_0,
      error_trng => error_trng,
      error_trng_reg_reg => BR_i_66_n_0,
      error_trng_reg_reg_0 => error_trng_reg_reg,
      rng_ready => rng_ready,
      rng_reg(63 downto 0) => trng_out(63 downto 0),
      stat_error => stat_error
    );
TRO: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO
     port map (
      en => enable_TRO,
      rng_ready => rng_ready,
      rng_reg(63 downto 0) => trng_out(63 downto 0)
    );
\addra_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(22),
      I1 => control_low_word(7),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(7),
      O => \command_reg0_reg[32]\(3)
    );
\addra_carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(21),
      I1 => control_low_word(6),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(6),
      O => \command_reg0_reg[32]\(2)
    );
\addra_carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(20),
      I1 => control_low_word(5),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(5),
      O => \command_reg0_reg[32]\(1)
    );
\addra_carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(19),
      I1 => control_low_word(4),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(4),
      O => \command_reg0_reg[32]\(0)
    );
\addra_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(24),
      I1 => control_low_word(9),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(9),
      O => S(1)
    );
\addra_carry__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(23),
      I1 => control_low_word(8),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(8),
      O => S(0)
    );
addra_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(18),
      I1 => control_low_word(3),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(3),
      O => \command_reg0_reg[28]\(3)
    );
addra_carry_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(17),
      I1 => control_low_word(2),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(2),
      O => \command_reg0_reg[28]\(2)
    );
addra_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(16),
      I1 => control_low_word(1),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(1),
      O => \command_reg0_reg[28]\(1)
    );
addra_carry_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"56A6"
    )
        port map (
      I0 => Q(15),
      I1 => control_low_word(0),
      I2 => BR_i_66_n_0,
      I3 => write_address_reg(0),
      O => \command_reg0_reg[28]\(0)
    );
bitgen_done_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => bitgen_done,
      CO(2) => bitgen_done_carry_n_1,
      CO(1) => bitgen_done_carry_n_2,
      CO(0) => bitgen_done_carry_n_3,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_bitgen_done_carry_O_UNCONNECTED(3 downto 0),
      S(3) => bitgen_done_carry_i_1_n_0,
      S(2) => bitgen_done_carry_i_2_n_0,
      S(1) => bitgen_done_carry_i_3_n_0,
      S(0) => bitgen_done_carry_i_4_n_0
    );
bitgen_done_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => Q(14),
      I1 => write_address_reg(9),
      O => bitgen_done_carry_i_1_n_0
    );
bitgen_done_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => write_address_reg(6),
      I1 => Q(11),
      I2 => write_address_reg(7),
      I3 => Q(12),
      I4 => Q(13),
      I5 => write_address_reg(8),
      O => bitgen_done_carry_i_2_n_0
    );
bitgen_done_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => write_address_reg(4),
      I1 => Q(9),
      I2 => write_address_reg(5),
      I3 => Q(10),
      I4 => Q(8),
      I5 => write_address_reg(3),
      O => bitgen_done_carry_i_3_n_0
    );
bitgen_done_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => Q(7),
      I1 => write_address_reg(2),
      I2 => write_address_reg(0),
      I3 => Q(5),
      I4 => write_address_reg(1),
      I5 => Q(6),
      O => bitgen_done_carry_i_4_n_0
    );
enable_TRO_for_bitgen_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000001000"
    )
        port map (
      I0 => Q(0),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      I5 => bitgen_done,
      O => enable_TRO_for_bitgen_i_1_n_0
    );
enable_TRO_for_bitgen_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => enable_TRO_for_bitgen_i_1_n_0,
      Q => enable_TRO_for_bitgen,
      R => '0'
    );
error_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => stat_error,
      Q => error_trng,
      R => '0'
    );
write_address1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => write_address1_carry_n_0,
      CO(2) => write_address1_carry_n_1,
      CO(1) => write_address1_carry_n_2,
      CO(0) => write_address1_carry_n_3,
      CYINIT => '0',
      DI(3) => write_address1_carry_i_1_n_0,
      DI(2) => write_address1_carry_i_2_n_0,
      DI(1) => write_address1_carry_i_3_n_0,
      DI(0) => write_address1_carry_i_4_n_0,
      O(3 downto 0) => NLW_write_address1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => write_address1_carry_i_5_n_0,
      S(2) => write_address1_carry_i_6_n_0,
      S(1) => write_address1_carry_i_7_n_0,
      S(0) => write_address1_carry_i_8_n_0
    );
\write_address1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => write_address1_carry_n_0,
      CO(3 downto 1) => \NLW_write_address1_carry__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => write_address1,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => \write_address1_carry__0_i_1_n_0\,
      O(3 downto 0) => \NLW_write_address1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3 downto 1) => B"000",
      S(0) => \write_address1_carry__0_i_2_n_0\
    );
\write_address1_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4D44"
    )
        port map (
      I0 => write_address_reg(9),
      I1 => Q(14),
      I2 => write_address_reg(8),
      I3 => Q(13),
      O => \write_address1_carry__0_i_1_n_0\
    );
\write_address1_carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => Q(14),
      I1 => write_address_reg(9),
      I2 => Q(13),
      I3 => write_address_reg(8),
      O => \write_address1_carry__0_i_2_n_0\
    );
write_address1_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => write_address_reg(7),
      I1 => Q(12),
      I2 => Q(11),
      I3 => write_address_reg(6),
      O => write_address1_carry_i_1_n_0
    );
write_address1_carry_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => write_address_reg(5),
      I1 => Q(10),
      I2 => Q(9),
      I3 => write_address_reg(4),
      O => write_address1_carry_i_2_n_0
    );
write_address1_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => write_address_reg(3),
      I1 => Q(8),
      I2 => Q(7),
      I3 => write_address_reg(2),
      O => write_address1_carry_i_3_n_0
    );
write_address1_carry_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"44D4"
    )
        port map (
      I0 => write_address_reg(1),
      I1 => Q(6),
      I2 => Q(5),
      I3 => write_address_reg(0),
      O => write_address1_carry_i_4_n_0
    );
write_address1_carry_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => Q(12),
      I1 => write_address_reg(7),
      I2 => Q(11),
      I3 => write_address_reg(6),
      O => write_address1_carry_i_5_n_0
    );
write_address1_carry_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => Q(10),
      I1 => write_address_reg(5),
      I2 => Q(9),
      I3 => write_address_reg(4),
      O => write_address1_carry_i_6_n_0
    );
write_address1_carry_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => Q(7),
      I1 => write_address_reg(2),
      I2 => Q(8),
      I3 => write_address_reg(3),
      O => write_address1_carry_i_7_n_0
    );
write_address1_carry_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => Q(6),
      I1 => write_address_reg(1),
      I2 => Q(5),
      I3 => write_address_reg(0),
      O => write_address1_carry_i_8_n_0
    );
\write_address[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => write_address_reg(0),
      I1 => write_address1,
      I2 => trng_wea,
      O => \write_address[0]_i_1_n_0\
    );
\write_address[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => write_address_reg(1),
      I1 => write_address_reg(0),
      I2 => trng_wea,
      I3 => write_address1,
      O => \write_address[1]_i_1_n_0\
    );
\write_address[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => write_address_reg(2),
      I1 => write_address_reg(1),
      I2 => write_address1,
      I3 => trng_wea,
      I4 => write_address_reg(0),
      O => \write_address[2]_i_1_n_0\
    );
\write_address[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0220"
    )
        port map (
      I0 => BR_i_66_n_0,
      I1 => Q(0),
      I2 => write_address_reg(3),
      I3 => \write_address[3]_i_2_n_0\,
      O => \write_address[3]_i_1_n_0\
    );
\write_address[3]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => write_address_reg(1),
      I1 => write_address1,
      I2 => trng_wea,
      I3 => write_address_reg(0),
      I4 => write_address_reg(2),
      O => \write_address[3]_i_2_n_0\
    );
\write_address[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => write_address_reg(4),
      I1 => \write_address[7]_i_2_n_0\,
      O => \write_address[4]_i_1_n_0\
    );
\write_address[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => write_address_reg(5),
      I1 => write_address_reg(4),
      I2 => \write_address[7]_i_2_n_0\,
      O => \write_address[5]_i_1_n_0\
    );
\write_address[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => write_address_reg(6),
      I1 => write_address_reg(5),
      I2 => \write_address[7]_i_2_n_0\,
      I3 => write_address_reg(4),
      O => \write_address[6]_i_1_n_0\
    );
\write_address[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => write_address_reg(7),
      I1 => write_address_reg(6),
      I2 => write_address_reg(4),
      I3 => \write_address[7]_i_2_n_0\,
      I4 => write_address_reg(5),
      O => \write_address[7]_i_1_n_0\
    );
\write_address[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8000000000000000"
    )
        port map (
      I0 => write_address_reg(2),
      I1 => write_address_reg(0),
      I2 => trng_wea,
      I3 => write_address1,
      I4 => write_address_reg(1),
      I5 => write_address_reg(3),
      O => \write_address[7]_i_2_n_0\
    );
\write_address[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0600"
    )
        port map (
      I0 => \write_address[8]_i_2_n_0\,
      I1 => write_address_reg(8),
      I2 => Q(0),
      I3 => BR_i_66_n_0,
      O => \write_address[8]_i_1_n_0\
    );
\write_address[8]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => write_address_reg(6),
      I1 => write_address_reg(4),
      I2 => \write_address[7]_i_2_n_0\,
      I3 => write_address_reg(5),
      I4 => write_address_reg(7),
      O => \write_address[8]_i_2_n_0\
    );
\write_address[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => write_address_reg(9),
      I1 => \write_address[8]_i_2_n_0\,
      I2 => write_address_reg(8),
      O => \write_address[9]_i_1_n_0\
    );
\write_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[0]_i_1_n_0\,
      Q => write_address_reg(0),
      R => trng_rst
    );
\write_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[1]_i_1_n_0\,
      Q => write_address_reg(1),
      R => trng_rst
    );
\write_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[2]_i_1_n_0\,
      Q => write_address_reg(2),
      R => trng_rst
    );
\write_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[3]_i_1_n_0\,
      Q => write_address_reg(3),
      R => '0'
    );
\write_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[4]_i_1_n_0\,
      Q => write_address_reg(4),
      R => trng_rst
    );
\write_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[5]_i_1_n_0\,
      Q => write_address_reg(5),
      R => trng_rst
    );
\write_address_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[6]_i_1_n_0\,
      Q => write_address_reg(6),
      R => trng_rst
    );
\write_address_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[7]_i_1_n_0\,
      Q => write_address_reg(7),
      R => trng_rst
    );
\write_address_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[8]_i_1_n_0\,
      Q => write_address_reg(8),
      R => '0'
    );
\write_address_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \write_address[9]_i_1_n_0\,
      Q => write_address_reg(9),
      R => trng_rst
    );
write_rng_data_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFEFFF"
    )
        port map (
      I0 => Q(0),
      I1 => Q(3),
      I2 => Q(4),
      I3 => Q(1),
      I4 => Q(2),
      O => trng_rst
    );
write_rng_data_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => write_rng_data0,
      Q => trng_wea,
      R => trng_rst
    );
end STRUCTURE;
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`protect key_block
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`protect end_protected
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM is
  port (
    a : in STD_LOGIC_VECTOR ( 5 downto 0 );
    d : in STD_LOGIC_VECTOR ( 36 downto 0 );
    dpra : in STD_LOGIC_VECTOR ( 5 downto 0 );
    clk : in STD_LOGIC;
    we : in STD_LOGIC;
    qdpo_clk : in STD_LOGIC;
    qdpo : out STD_LOGIC_VECTOR ( 36 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM : entity is "INS_RAM,dist_mem_gen_v8_0_13,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM : entity is "INS_RAM";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM : entity is "dist_mem_gen_v8_0_13,Vivado 2019.1";
end cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM is
  signal \<const0>\ : STD_LOGIC;
  signal \^qdpo\ : STD_LOGIC_VECTOR ( 36 downto 0 );
  signal NLW_U0_dpo_UNCONNECTED : STD_LOGIC_VECTOR ( 36 downto 0 );
  signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 15 );
  signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 36 downto 0 );
  signal NLW_U0_spo_UNCONNECTED : STD_LOGIC_VECTOR ( 36 downto 0 );
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynq";
  attribute C_HAS_CLK : integer;
  attribute C_HAS_CLK of U0 : label is 1;
  attribute C_HAS_D : integer;
  attribute C_HAS_D of U0 : label is 1;
  attribute C_HAS_DPO : integer;
  attribute C_HAS_DPO of U0 : label is 0;
  attribute C_HAS_DPRA : integer;
  attribute C_HAS_DPRA of U0 : label is 1;
  attribute C_HAS_QDPO : integer;
  attribute C_HAS_QDPO of U0 : label is 1;
  attribute C_HAS_QDPO_CE : integer;
  attribute C_HAS_QDPO_CE of U0 : label is 0;
  attribute C_HAS_QDPO_CLK : integer;
  attribute C_HAS_QDPO_CLK of U0 : label is 1;
  attribute C_HAS_QDPO_RST : integer;
  attribute C_HAS_QDPO_RST of U0 : label is 0;
  attribute C_HAS_QDPO_SRST : integer;
  attribute C_HAS_QDPO_SRST of U0 : label is 0;
  attribute C_HAS_QSPO : integer;
  attribute C_HAS_QSPO of U0 : label is 0;
  attribute C_HAS_QSPO_RST : integer;
  attribute C_HAS_QSPO_RST of U0 : label is 0;
  attribute C_HAS_QSPO_SRST : integer;
  attribute C_HAS_QSPO_SRST of U0 : label is 0;
  attribute C_HAS_SPO : integer;
  attribute C_HAS_SPO of U0 : label is 0;
  attribute C_HAS_WE : integer;
  attribute C_HAS_WE of U0 : label is 1;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 4;
  attribute C_REG_DPRA_INPUT : integer;
  attribute C_REG_DPRA_INPUT of U0 : label is 0;
  attribute c_addr_width : integer;
  attribute c_addr_width of U0 : label is 6;
  attribute c_depth : integer;
  attribute c_depth of U0 : label is 64;
  attribute c_has_i_ce : integer;
  attribute c_has_i_ce of U0 : label is 0;
  attribute c_has_qspo_ce : integer;
  attribute c_has_qspo_ce of U0 : label is 0;
  attribute c_mem_init_file : string;
  attribute c_mem_init_file of U0 : label is "no_coe_file_loaded";
  attribute c_parser_type : integer;
  attribute c_parser_type of U0 : label is 1;
  attribute c_pipeline_stages : integer;
  attribute c_pipeline_stages of U0 : label is 0;
  attribute c_qce_joined : integer;
  attribute c_qce_joined of U0 : label is 0;
  attribute c_qualify_we : integer;
  attribute c_qualify_we of U0 : label is 0;
  attribute c_read_mif : integer;
  attribute c_read_mif of U0 : label is 0;
  attribute c_reg_a_d_inputs : integer;
  attribute c_reg_a_d_inputs of U0 : label is 0;
  attribute c_sync_enable : integer;
  attribute c_sync_enable of U0 : label is 1;
  attribute c_width : integer;
  attribute c_width of U0 : label is 37;
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
begin
  qdpo(36 downto 25) <= \^qdpo\(36 downto 25);
  qdpo(24) <= \<const0>\;
  qdpo(23) <= \<const0>\;
  qdpo(22) <= \<const0>\;
  qdpo(21) <= \<const0>\;
  qdpo(20) <= \<const0>\;
  qdpo(19) <= \<const0>\;
  qdpo(18) <= \<const0>\;
  qdpo(17) <= \<const0>\;
  qdpo(16) <= \<const0>\;
  qdpo(15) <= \<const0>\;
  qdpo(14 downto 0) <= \^qdpo\(14 downto 0);
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_dist_mem_gen_v8_0_13
     port map (
      a(5 downto 0) => a(5 downto 0),
      clk => '0',
      d(36 downto 0) => d(36 downto 0),
      dpo(36 downto 0) => NLW_U0_dpo_UNCONNECTED(36 downto 0),
      dpra(5 downto 0) => dpra(5 downto 0),
      i_ce => '1',
      qdpo(36 downto 25) => \^qdpo\(36 downto 25),
      qdpo(24 downto 15) => NLW_U0_qdpo_UNCONNECTED(24 downto 15),
      qdpo(14 downto 0) => \^qdpo\(14 downto 0),
      qdpo_ce => '1',
      qdpo_clk => qdpo_clk,
      qdpo_rst => '0',
      qdpo_srst => '0',
      qspo(36 downto 0) => NLW_U0_qspo_UNCONNECTED(36 downto 0),
      qspo_ce => '1',
      qspo_rst => '0',
      qspo_srst => '0',
      spo(36 downto 0) => NLW_U0_spo_UNCONNECTED(36 downto 0),
      we => we
    );
end STRUCTURE;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control is
  port (
    qdpo : out STD_LOGIC_VECTOR ( 25 downto 0 );
    D : out STD_LOGIC_VECTOR ( 30 downto 0 );
    control_low_word : in STD_LOGIC_VECTOR ( 7 downto 0 );
    \^d\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    clk : in STD_LOGIC;
    control_high_word : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_sequential_state_reg[1]_0\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control : entity is "ISA_control";
end cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control is
  signal \^d_1\ : STD_LOGIC_VECTOR ( 30 downto 0 );
  signal \FSM_sequential_state[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_sequential_state[2]_i_2_n_0\ : STD_LOGIC;
  signal IR_address0 : STD_LOGIC;
  signal \IR_address[5]_i_2_n_0\ : STD_LOGIC;
  signal IR_address_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal command_we1 : STD_LOGIC;
  signal \cycle_count[0]_i_2_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[0]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[24]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[28]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[28]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[28]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \cycle_count_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal nextstate : STD_LOGIC_VECTOR ( 2 downto 1 );
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^qdpo\ : STD_LOGIC_VECTOR ( 25 downto 0 );
  signal state : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal wea_ext_ISA : STD_LOGIC;
  signal NLW_IR_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 15 );
  signal \NLW_cycle_count_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_cycle_count_reg[28]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_sequential_state[0]_i_1\ : label is "soft_lutpair35";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[0]\ : label is "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[1]\ : label is "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111";
  attribute FSM_ENCODED_STATES of \FSM_sequential_state_reg[2]\ : label is "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111";
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of IR : label is "INS_RAM,dist_mem_gen_v8_0_13,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of IR : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of IR : label is "dist_mem_gen_v8_0_13,Vivado 2019.1";
  attribute SOFT_HLUTNM of \IR_address[1]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \IR_address[2]_i_1\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \IR_address[3]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \IR_address[4]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \status[0]_i_1\ : label is "soft_lutpair35";
begin
  D(30 downto 0) <= \^d_1\(30 downto 0);
  qdpo(25 downto 0) <= \^qdpo\(25 downto 0);
\FSM_sequential_state[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F100FFFF"
    )
        port map (
      I0 => \FSM_sequential_state_reg[1]_0\,
      I1 => \FSM_sequential_state[1]_i_3_n_0\,
      I2 => state(1),
      I3 => state(2),
      I4 => state(0),
      O => \FSM_sequential_state[0]_i_1_n_0\
    );
\FSM_sequential_state[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFF0EE0000FFFF00"
    )
        port map (
      I0 => \FSM_sequential_state_reg[1]_0\,
      I1 => \FSM_sequential_state[1]_i_3_n_0\,
      I2 => \FSM_sequential_state[2]_i_2_n_0\,
      I3 => state(0),
      I4 => state(1),
      I5 => state(2),
      O => nextstate(1)
    );
\FSM_sequential_state[1]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF80000001"
    )
        port map (
      I0 => \^qdpo\(2),
      I1 => \^qdpo\(3),
      I2 => \^qdpo\(4),
      I3 => \^qdpo\(0),
      I4 => \^qdpo\(1),
      I5 => command_we1,
      O => \FSM_sequential_state[1]_i_3_n_0\
    );
\FSM_sequential_state[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FC8C"
    )
        port map (
      I0 => \FSM_sequential_state[2]_i_2_n_0\,
      I1 => state(2),
      I2 => state(1),
      I3 => state(0),
      O => nextstate(2)
    );
\FSM_sequential_state[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \^qdpo\(4),
      I1 => \^qdpo\(3),
      I2 => \^qdpo\(1),
      I3 => \^qdpo\(0),
      I4 => \^qdpo\(2),
      O => \FSM_sequential_state[2]_i_2_n_0\
    );
\FSM_sequential_state_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \FSM_sequential_state[0]_i_1_n_0\,
      Q => state(0),
      R => control_high_word(0)
    );
\FSM_sequential_state_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => nextstate(1),
      Q => state(1),
      R => control_high_word(0)
    );
\FSM_sequential_state_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => nextstate(2),
      Q => state(2),
      R => control_high_word(0)
    );
IR: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM
     port map (
      a(5 downto 0) => control_low_word(5 downto 0),
      clk => '0',
      d(36 downto 0) => \^d\(36 downto 0),
      dpra(5 downto 0) => IR_address_reg(5 downto 0),
      qdpo(36) => command_we1,
      qdpo(35 downto 25) => \^qdpo\(25 downto 15),
      qdpo(24 downto 15) => NLW_IR_qdpo_UNCONNECTED(24 downto 15),
      qdpo(14 downto 0) => \^qdpo\(14 downto 0),
      qdpo_clk => clk,
      we => wea_ext_ISA
    );
\IR_address[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => IR_address_reg(0),
      O => p_0_in(0)
    );
\IR_address[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => IR_address_reg(1),
      I1 => IR_address_reg(0),
      O => p_0_in(1)
    );
\IR_address[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => IR_address_reg(2),
      I1 => IR_address_reg(0),
      I2 => IR_address_reg(1),
      O => p_0_in(2)
    );
\IR_address[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6AAA"
    )
        port map (
      I0 => IR_address_reg(3),
      I1 => IR_address_reg(1),
      I2 => IR_address_reg(0),
      I3 => IR_address_reg(2),
      O => p_0_in(3)
    );
\IR_address[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"6AAAAAAA"
    )
        port map (
      I0 => IR_address_reg(4),
      I1 => IR_address_reg(2),
      I2 => IR_address_reg(0),
      I3 => IR_address_reg(1),
      I4 => IR_address_reg(3),
      O => p_0_in(4)
    );
\IR_address[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => control_high_word(0),
      I1 => control_high_word(1),
      O => IR_address0
    );
\IR_address[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"41"
    )
        port map (
      I0 => state(0),
      I1 => state(2),
      I2 => state(1),
      O => \IR_address[5]_i_2_n_0\
    );
\IR_address[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6AAAAAAAAAAAAAAA"
    )
        port map (
      I0 => IR_address_reg(5),
      I1 => IR_address_reg(3),
      I2 => IR_address_reg(1),
      I3 => IR_address_reg(0),
      I4 => IR_address_reg(2),
      I5 => IR_address_reg(4),
      O => p_0_in(5)
    );
\IR_address_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(0),
      Q => IR_address_reg(0),
      R => IR_address0
    );
\IR_address_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(1),
      Q => IR_address_reg(1),
      R => IR_address0
    );
\IR_address_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(2),
      Q => IR_address_reg(2),
      R => IR_address0
    );
\IR_address_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(3),
      Q => IR_address_reg(3),
      R => IR_address0
    );
\IR_address_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(4),
      Q => IR_address_reg(4),
      R => IR_address0
    );
\IR_address_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \IR_address[5]_i_2_n_0\,
      D => p_0_in(5),
      Q => IR_address_reg(5),
      R => IR_address0
    );
IR_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => control_low_word(7),
      I1 => control_low_word(6),
      O => wea_ext_ISA
    );
\cycle_count[0]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^d_1\(1),
      O => \cycle_count[0]_i_2_n_0\
    );
\cycle_count_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[0]_i_1_n_7\,
      Q => \^d_1\(1),
      R => control_high_word(0)
    );
\cycle_count_reg[0]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \cycle_count_reg[0]_i_1_n_0\,
      CO(2) => \cycle_count_reg[0]_i_1_n_1\,
      CO(1) => \cycle_count_reg[0]_i_1_n_2\,
      CO(0) => \cycle_count_reg[0]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \cycle_count_reg[0]_i_1_n_4\,
      O(2) => \cycle_count_reg[0]_i_1_n_5\,
      O(1) => \cycle_count_reg[0]_i_1_n_6\,
      O(0) => \cycle_count_reg[0]_i_1_n_7\,
      S(3 downto 1) => \^d_1\(4 downto 2),
      S(0) => \cycle_count[0]_i_2_n_0\
    );
\cycle_count_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[8]_i_1_n_5\,
      Q => \^d_1\(11),
      R => control_high_word(0)
    );
\cycle_count_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[8]_i_1_n_4\,
      Q => \^d_1\(12),
      R => control_high_word(0)
    );
\cycle_count_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[12]_i_1_n_7\,
      Q => \^d_1\(13),
      R => control_high_word(0)
    );
\cycle_count_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[8]_i_1_n_0\,
      CO(3) => \cycle_count_reg[12]_i_1_n_0\,
      CO(2) => \cycle_count_reg[12]_i_1_n_1\,
      CO(1) => \cycle_count_reg[12]_i_1_n_2\,
      CO(0) => \cycle_count_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[12]_i_1_n_4\,
      O(2) => \cycle_count_reg[12]_i_1_n_5\,
      O(1) => \cycle_count_reg[12]_i_1_n_6\,
      O(0) => \cycle_count_reg[12]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(16 downto 13)
    );
\cycle_count_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[12]_i_1_n_6\,
      Q => \^d_1\(14),
      R => control_high_word(0)
    );
\cycle_count_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[12]_i_1_n_5\,
      Q => \^d_1\(15),
      R => control_high_word(0)
    );
\cycle_count_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[12]_i_1_n_4\,
      Q => \^d_1\(16),
      R => control_high_word(0)
    );
\cycle_count_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[16]_i_1_n_7\,
      Q => \^d_1\(17),
      R => control_high_word(0)
    );
\cycle_count_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[12]_i_1_n_0\,
      CO(3) => \cycle_count_reg[16]_i_1_n_0\,
      CO(2) => \cycle_count_reg[16]_i_1_n_1\,
      CO(1) => \cycle_count_reg[16]_i_1_n_2\,
      CO(0) => \cycle_count_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[16]_i_1_n_4\,
      O(2) => \cycle_count_reg[16]_i_1_n_5\,
      O(1) => \cycle_count_reg[16]_i_1_n_6\,
      O(0) => \cycle_count_reg[16]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(20 downto 17)
    );
\cycle_count_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[16]_i_1_n_6\,
      Q => \^d_1\(18),
      R => control_high_word(0)
    );
\cycle_count_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[16]_i_1_n_5\,
      Q => \^d_1\(19),
      R => control_high_word(0)
    );
\cycle_count_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[16]_i_1_n_4\,
      Q => \^d_1\(20),
      R => control_high_word(0)
    );
\cycle_count_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[0]_i_1_n_6\,
      Q => \^d_1\(2),
      R => control_high_word(0)
    );
\cycle_count_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[20]_i_1_n_7\,
      Q => \^d_1\(21),
      R => control_high_word(0)
    );
\cycle_count_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[16]_i_1_n_0\,
      CO(3) => \cycle_count_reg[20]_i_1_n_0\,
      CO(2) => \cycle_count_reg[20]_i_1_n_1\,
      CO(1) => \cycle_count_reg[20]_i_1_n_2\,
      CO(0) => \cycle_count_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[20]_i_1_n_4\,
      O(2) => \cycle_count_reg[20]_i_1_n_5\,
      O(1) => \cycle_count_reg[20]_i_1_n_6\,
      O(0) => \cycle_count_reg[20]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(24 downto 21)
    );
\cycle_count_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[20]_i_1_n_6\,
      Q => \^d_1\(22),
      R => control_high_word(0)
    );
\cycle_count_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[20]_i_1_n_5\,
      Q => \^d_1\(23),
      R => control_high_word(0)
    );
\cycle_count_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[20]_i_1_n_4\,
      Q => \^d_1\(24),
      R => control_high_word(0)
    );
\cycle_count_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[24]_i_1_n_7\,
      Q => \^d_1\(25),
      R => control_high_word(0)
    );
\cycle_count_reg[24]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[20]_i_1_n_0\,
      CO(3) => \cycle_count_reg[24]_i_1_n_0\,
      CO(2) => \cycle_count_reg[24]_i_1_n_1\,
      CO(1) => \cycle_count_reg[24]_i_1_n_2\,
      CO(0) => \cycle_count_reg[24]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[24]_i_1_n_4\,
      O(2) => \cycle_count_reg[24]_i_1_n_5\,
      O(1) => \cycle_count_reg[24]_i_1_n_6\,
      O(0) => \cycle_count_reg[24]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(28 downto 25)
    );
\cycle_count_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[24]_i_1_n_6\,
      Q => \^d_1\(26),
      R => control_high_word(0)
    );
\cycle_count_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[24]_i_1_n_5\,
      Q => \^d_1\(27),
      R => control_high_word(0)
    );
\cycle_count_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[24]_i_1_n_4\,
      Q => \^d_1\(28),
      R => control_high_word(0)
    );
\cycle_count_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[28]_i_1_n_7\,
      Q => \^d_1\(29),
      R => control_high_word(0)
    );
\cycle_count_reg[28]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[24]_i_1_n_0\,
      CO(3 downto 1) => \NLW_cycle_count_reg[28]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \cycle_count_reg[28]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_cycle_count_reg[28]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \cycle_count_reg[28]_i_1_n_6\,
      O(0) => \cycle_count_reg[28]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1 downto 0) => \^d_1\(30 downto 29)
    );
\cycle_count_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[28]_i_1_n_6\,
      Q => \^d_1\(30),
      R => control_high_word(0)
    );
\cycle_count_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[0]_i_1_n_5\,
      Q => \^d_1\(3),
      R => control_high_word(0)
    );
\cycle_count_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[0]_i_1_n_4\,
      Q => \^d_1\(4),
      R => control_high_word(0)
    );
\cycle_count_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[4]_i_1_n_7\,
      Q => \^d_1\(5),
      R => control_high_word(0)
    );
\cycle_count_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[0]_i_1_n_0\,
      CO(3) => \cycle_count_reg[4]_i_1_n_0\,
      CO(2) => \cycle_count_reg[4]_i_1_n_1\,
      CO(1) => \cycle_count_reg[4]_i_1_n_2\,
      CO(0) => \cycle_count_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[4]_i_1_n_4\,
      O(2) => \cycle_count_reg[4]_i_1_n_5\,
      O(1) => \cycle_count_reg[4]_i_1_n_6\,
      O(0) => \cycle_count_reg[4]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(8 downto 5)
    );
\cycle_count_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[4]_i_1_n_6\,
      Q => \^d_1\(6),
      R => control_high_word(0)
    );
\cycle_count_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[4]_i_1_n_5\,
      Q => \^d_1\(7),
      R => control_high_word(0)
    );
\cycle_count_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[4]_i_1_n_4\,
      Q => \^d_1\(8),
      R => control_high_word(0)
    );
\cycle_count_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[8]_i_1_n_7\,
      Q => \^d_1\(9),
      R => control_high_word(0)
    );
\cycle_count_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \cycle_count_reg[4]_i_1_n_0\,
      CO(3) => \cycle_count_reg[8]_i_1_n_0\,
      CO(2) => \cycle_count_reg[8]_i_1_n_1\,
      CO(1) => \cycle_count_reg[8]_i_1_n_2\,
      CO(0) => \cycle_count_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \cycle_count_reg[8]_i_1_n_4\,
      O(2) => \cycle_count_reg[8]_i_1_n_5\,
      O(1) => \cycle_count_reg[8]_i_1_n_6\,
      O(0) => \cycle_count_reg[8]_i_1_n_7\,
      S(3 downto 0) => \^d_1\(12 downto 9)
    );
\cycle_count_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => \cycle_count_reg[8]_i_1_n_6\,
      Q => \^d_1\(10),
      R => control_high_word(0)
    );
\status[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => state(2),
      I1 => state(0),
      I2 => state(1),
      O => \^d_1\(0)
    );
end STRUCTURE;
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 is
  port (
    clka : in STD_LOGIC;
    wea : in STD_LOGIC_VECTOR ( 0 to 0 );
    addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
    dina : in STD_LOGIC_VECTOR ( 63 downto 0 );
    clkb : in STD_LOGIC;
    addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 )
  );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 : entity is "BRAM64_1024,blk_mem_gen_v8_4_4,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 : entity is "yes";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 : entity is "BRAM64_1024";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 : entity is "blk_mem_gen_v8_4_4,Vivado 2020.2";
end cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 is
  signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute C_ADDRA_WIDTH : integer;
  attribute C_ADDRA_WIDTH of U0 : label is 10;
  attribute C_ADDRB_WIDTH : integer;
  attribute C_ADDRB_WIDTH of U0 : label is 10;
  attribute C_ALGORITHM : integer;
  attribute C_ALGORITHM of U0 : label is 1;
  attribute C_AXI_ID_WIDTH : integer;
  attribute C_AXI_ID_WIDTH of U0 : label is 4;
  attribute C_AXI_SLAVE_TYPE : integer;
  attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
  attribute C_AXI_TYPE : integer;
  attribute C_AXI_TYPE of U0 : label is 1;
  attribute C_BYTE_SIZE : integer;
  attribute C_BYTE_SIZE of U0 : label is 9;
  attribute C_COMMON_CLK : integer;
  attribute C_COMMON_CLK of U0 : label is 1;
  attribute C_COUNT_18K_BRAM : string;
  attribute C_COUNT_18K_BRAM of U0 : label is "0";
  attribute C_COUNT_36K_BRAM : string;
  attribute C_COUNT_36K_BRAM of U0 : label is "2";
  attribute C_CTRL_ECC_ALGO : string;
  attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of U0 : label is "0";
  attribute C_DISABLE_WARN_BHV_COLL : integer;
  attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
  attribute C_DISABLE_WARN_BHV_RANGE : integer;
  attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of U0 : label is "./";
  attribute C_ENABLE_32BIT_ADDRESS : integer;
  attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
  attribute C_EN_DEEPSLEEP_PIN : integer;
  attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
  attribute C_EN_ECC_PIPE : integer;
  attribute C_EN_ECC_PIPE of U0 : label is 0;
  attribute C_EN_RDADDRA_CHG : integer;
  attribute C_EN_RDADDRA_CHG of U0 : label is 0;
  attribute C_EN_RDADDRB_CHG : integer;
  attribute C_EN_RDADDRB_CHG of U0 : label is 0;
  attribute C_EN_SAFETY_CKT : integer;
  attribute C_EN_SAFETY_CKT of U0 : label is 0;
  attribute C_EN_SHUTDOWN_PIN : integer;
  attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
  attribute C_EN_SLEEP_PIN : integer;
  attribute C_EN_SLEEP_PIN of U0 : label is 0;
  attribute C_EST_POWER_SUMMARY : string;
  attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP     :     10.882749 mW";
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "zynq";
  attribute C_HAS_AXI_ID : integer;
  attribute C_HAS_AXI_ID of U0 : label is 0;
  attribute C_HAS_ENA : integer;
  attribute C_HAS_ENA of U0 : label is 0;
  attribute C_HAS_ENB : integer;
  attribute C_HAS_ENB of U0 : label is 0;
  attribute C_HAS_INJECTERR : integer;
  attribute C_HAS_INJECTERR of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
  attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
  attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_HAS_REGCEA : integer;
  attribute C_HAS_REGCEA of U0 : label is 0;
  attribute C_HAS_REGCEB : integer;
  attribute C_HAS_REGCEB of U0 : label is 0;
  attribute C_HAS_RSTA : integer;
  attribute C_HAS_RSTA of U0 : label is 0;
  attribute C_HAS_RSTB : integer;
  attribute C_HAS_RSTB of U0 : label is 0;
  attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
  attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
  attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
  attribute C_INITA_VAL : string;
  attribute C_INITA_VAL of U0 : label is "0";
  attribute C_INITB_VAL : string;
  attribute C_INITB_VAL of U0 : label is "0";
  attribute C_INIT_FILE : string;
  attribute C_INIT_FILE of U0 : label is "BRAM64_1024.mem";
  attribute C_INIT_FILE_NAME : string;
  attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
  attribute C_INTERFACE_TYPE : integer;
  attribute C_INTERFACE_TYPE of U0 : label is 0;
  attribute C_LOAD_INIT_FILE : integer;
  attribute C_LOAD_INIT_FILE of U0 : label is 0;
  attribute C_MEM_TYPE : integer;
  attribute C_MEM_TYPE of U0 : label is 1;
  attribute C_MUX_PIPELINE_STAGES : integer;
  attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
  attribute C_PRIM_TYPE : integer;
  attribute C_PRIM_TYPE of U0 : label is 1;
  attribute C_READ_DEPTH_A : integer;
  attribute C_READ_DEPTH_A of U0 : label is 1024;
  attribute C_READ_DEPTH_B : integer;
  attribute C_READ_DEPTH_B of U0 : label is 1024;
  attribute C_READ_LATENCY_A : integer;
  attribute C_READ_LATENCY_A of U0 : label is 1;
  attribute C_READ_LATENCY_B : integer;
  attribute C_READ_LATENCY_B of U0 : label is 1;
  attribute C_READ_WIDTH_A : integer;
  attribute C_READ_WIDTH_A of U0 : label is 64;
  attribute C_READ_WIDTH_B : integer;
  attribute C_READ_WIDTH_B of U0 : label is 64;
  attribute C_RSTRAM_A : integer;
  attribute C_RSTRAM_A of U0 : label is 0;
  attribute C_RSTRAM_B : integer;
  attribute C_RSTRAM_B of U0 : label is 0;
  attribute C_RST_PRIORITY_A : string;
  attribute C_RST_PRIORITY_A of U0 : label is "CE";
  attribute C_RST_PRIORITY_B : string;
  attribute C_RST_PRIORITY_B of U0 : label is "CE";
  attribute C_SIM_COLLISION_CHECK : string;
  attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
  attribute C_USE_BRAM_BLOCK : integer;
  attribute C_USE_BRAM_BLOCK of U0 : label is 0;
  attribute C_USE_BYTE_WEA : integer;
  attribute C_USE_BYTE_WEA of U0 : label is 0;
  attribute C_USE_BYTE_WEB : integer;
  attribute C_USE_BYTE_WEB of U0 : label is 0;
  attribute C_USE_DEFAULT_DATA : integer;
  attribute C_USE_DEFAULT_DATA of U0 : label is 0;
  attribute C_USE_ECC : integer;
  attribute C_USE_ECC of U0 : label is 0;
  attribute C_USE_SOFTECC : integer;
  attribute C_USE_SOFTECC of U0 : label is 0;
  attribute C_USE_URAM : integer;
  attribute C_USE_URAM of U0 : label is 0;
  attribute C_WEA_WIDTH : integer;
  attribute C_WEA_WIDTH of U0 : label is 1;
  attribute C_WEB_WIDTH : integer;
  attribute C_WEB_WIDTH of U0 : label is 1;
  attribute C_WRITE_DEPTH_A : integer;
  attribute C_WRITE_DEPTH_A of U0 : label is 1024;
  attribute C_WRITE_DEPTH_B : integer;
  attribute C_WRITE_DEPTH_B of U0 : label is 1024;
  attribute C_WRITE_MODE_A : string;
  attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
  attribute C_WRITE_MODE_B : string;
  attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST";
  attribute C_WRITE_WIDTH_A : integer;
  attribute C_WRITE_WIDTH_A of U0 : label is 64;
  attribute C_WRITE_WIDTH_B : integer;
  attribute C_WRITE_WIDTH_B of U0 : label is 64;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "zynq";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute is_du_within_envelope : string;
  attribute is_du_within_envelope of U0 : label is "true";
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
  attribute X_INTERFACE_PARAMETER of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
  attribute X_INTERFACE_INFO of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
  attribute X_INTERFACE_INFO of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
  attribute X_INTERFACE_INFO of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
  attribute X_INTERFACE_INFO of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
  attribute X_INTERFACE_INFO of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_blk_mem_gen_v8_4_4
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(9 downto 0) => addrb(9 downto 0),
      clka => clka,
      clkb => '0',
      dbiterr => NLW_U0_dbiterr_UNCONNECTED,
      deepsleep => '0',
      dina(63 downto 0) => dina(63 downto 0),
      dinb(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      douta(63 downto 0) => NLW_U0_douta_UNCONNECTED(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      eccpipece => '0',
      ena => '0',
      enb => '0',
      injectdbiterr => '0',
      injectsbiterr => '0',
      rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
      regcea => '0',
      regceb => '0',
      rsta => '0',
      rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
      rstb => '0',
      rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
      s_aclk => '0',
      s_aresetn => '0',
      s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_arburst(1 downto 0) => B"00",
      s_axi_arid(3 downto 0) => B"0000",
      s_axi_arlen(7 downto 0) => B"00000000",
      s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
      s_axi_arsize(2 downto 0) => B"000",
      s_axi_arvalid => '0',
      s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
      s_axi_awburst(1 downto 0) => B"00",
      s_axi_awid(3 downto 0) => B"0000",
      s_axi_awlen(7 downto 0) => B"00000000",
      s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
      s_axi_awsize(2 downto 0) => B"000",
      s_axi_awvalid => '0',
      s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
      s_axi_bready => '0',
      s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
      s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
      s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
      s_axi_injectdbiterr => '0',
      s_axi_injectsbiterr => '0',
      s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
      s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
      s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
      s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
      s_axi_rready => '0',
      s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
      s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
      s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
      s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
      s_axi_wlast => '0',
      s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
      s_axi_wstrb(0) => '0',
      s_axi_wvalid => '0',
      sbiterr => NLW_U0_sbiterr_UNCONNECTED,
      shutdown => '0',
      sleep => '0',
      wea(0) => wea(0),
      web(0) => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore is
  port (
    doutb : out STD_LOGIC_VECTOR ( 63 downto 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \command_reg0_reg[0]_0\ : out STD_LOGIC;
    clk : in STD_LOGIC;
    \^d\ : in STD_LOGIC_VECTOR ( 36 downto 0 );
    dina_ext_high_word : in STD_LOGIC_VECTOR ( 26 downto 0 );
    control_low_word : in STD_LOGIC_VECTOR ( 11 downto 0 );
    control_high_word : in STD_LOGIC_VECTOR ( 0 to 0 );
    qdpo : in STD_LOGIC_VECTOR ( 25 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore : entity is "ComputeCore";
end cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore is
  signal \^d_1\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal OP1_or_OP2 : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal OP3 : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal RNG_n_66 : STD_LOGIC;
  signal RNG_n_67 : STD_LOGIC;
  signal RNG_n_68 : STD_LOGIC;
  signal RNG_n_69 : STD_LOGIC;
  signal RNG_n_70 : STD_LOGIC;
  signal RNG_n_71 : STD_LOGIC;
  signal RNG_n_72 : STD_LOGIC;
  signal RNG_n_73 : STD_LOGIC;
  signal RNG_n_74 : STD_LOGIC;
  signal RNG_n_75 : STD_LOGIC;
  signal RNG_n_76 : STD_LOGIC;
  signal addra : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \addra_carry__0_n_0\ : STD_LOGIC;
  signal \addra_carry__0_n_1\ : STD_LOGIC;
  signal \addra_carry__0_n_2\ : STD_LOGIC;
  signal \addra_carry__0_n_3\ : STD_LOGIC;
  signal \addra_carry__1_n_3\ : STD_LOGIC;
  signal addra_carry_n_0 : STD_LOGIC;
  signal addra_carry_n_1 : STD_LOGIC;
  signal addra_carry_n_2 : STD_LOGIC;
  signal addra_carry_n_3 : STD_LOGIC;
  signal addrb : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \addrb_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \addrb_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \addrb_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \addrb_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \addrb_carry__0_n_0\ : STD_LOGIC;
  signal \addrb_carry__0_n_1\ : STD_LOGIC;
  signal \addrb_carry__0_n_2\ : STD_LOGIC;
  signal \addrb_carry__0_n_3\ : STD_LOGIC;
  signal \addrb_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \addrb_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \addrb_carry__1_n_3\ : STD_LOGIC;
  signal addrb_carry_i_1_n_0 : STD_LOGIC;
  signal addrb_carry_i_2_n_0 : STD_LOGIC;
  signal addrb_carry_i_3_n_0 : STD_LOGIC;
  signal addrb_carry_i_4_n_0 : STD_LOGIC;
  signal addrb_carry_n_0 : STD_LOGIC;
  signal addrb_carry_n_1 : STD_LOGIC;
  signal addrb_carry_n_2 : STD_LOGIC;
  signal addrb_carry_n_3 : STD_LOGIC;
  signal \command_reg0_reg_n_0_[0]\ : STD_LOGIC;
  signal \command_reg0_reg_n_0_[1]\ : STD_LOGIC;
  signal \command_reg0_reg_n_0_[2]\ : STD_LOGIC;
  signal \command_reg0_reg_n_0_[3]\ : STD_LOGIC;
  signal \command_reg0_reg_n_0_[4]\ : STD_LOGIC;
  signal dina : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal error_trng_reg_i_2_n_0 : STD_LOGIC;
  signal wea : STD_LOGIC;
  signal \NLW_addra_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_addra_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_addrb_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_addrb_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of BR : label is "BRAM64_1024,blk_mem_gen_v8_4_4,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of BR : label is "yes";
  attribute x_core_info : string;
  attribute x_core_info of BR : label is "blk_mem_gen_v8_4_4,Vivado 2020.2";
  attribute ADDER_THRESHOLD : integer;
  attribute ADDER_THRESHOLD of addra_carry : label is 35;
  attribute ADDER_THRESHOLD of \addra_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \addra_carry__1\ : label is 35;
  attribute ADDER_THRESHOLD of addrb_carry : label is 35;
  attribute ADDER_THRESHOLD of \addrb_carry__0\ : label is 35;
  attribute ADDER_THRESHOLD of \addrb_carry__1\ : label is 35;
begin
  D(0) <= \^d_1\(0);
BR: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024
     port map (
      addra(9 downto 0) => addra(9 downto 0),
      addrb(9 downto 0) => addrb(9 downto 0),
      clka => clk,
      clkb => '0',
      dina(63 downto 0) => dina(63 downto 0),
      doutb(63 downto 0) => doutb(63 downto 0),
      wea(0) => wea
    );
RNG: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper
     port map (
      D(0) => \^d_1\(0),
      Q(24 downto 15) => OP3(9 downto 0),
      Q(14 downto 5) => OP1_or_OP2(9 downto 0),
      Q(4) => \command_reg0_reg_n_0_[4]\,
      Q(3) => \command_reg0_reg_n_0_[3]\,
      Q(2) => \command_reg0_reg_n_0_[2]\,
      Q(1) => \command_reg0_reg_n_0_[1]\,
      Q(0) => \command_reg0_reg_n_0_[0]\,
      S(1) => RNG_n_66,
      S(0) => RNG_n_67,
      clk => clk,
      \command_reg0_reg[0]\ => \command_reg0_reg[0]_0\,
      \command_reg0_reg[28]\(3) => RNG_n_68,
      \command_reg0_reg[28]\(2) => RNG_n_69,
      \command_reg0_reg[28]\(1) => RNG_n_70,
      \command_reg0_reg[28]\(0) => RNG_n_71,
      \command_reg0_reg[32]\(3) => RNG_n_72,
      \command_reg0_reg[32]\(2) => RNG_n_73,
      \command_reg0_reg[32]\(1) => RNG_n_74,
      \command_reg0_reg[32]\(0) => RNG_n_75,
      control_low_word(11 downto 0) => control_low_word(11 downto 0),
      \^d\(36 downto 0) => \^d\(36 downto 0),
      dina(63 downto 0) => dina(63 downto 0),
      dina_ext_high_word(26 downto 0) => dina_ext_high_word(26 downto 0),
      error_reg_0 => RNG_n_76,
      error_trng_reg_reg => error_trng_reg_i_2_n_0,
      wea(0) => wea
    );
addra_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => addra_carry_n_0,
      CO(2) => addra_carry_n_1,
      CO(1) => addra_carry_n_2,
      CO(0) => addra_carry_n_3,
      CYINIT => '0',
      DI(3 downto 0) => OP3(3 downto 0),
      O(3 downto 0) => addra(3 downto 0),
      S(3) => RNG_n_68,
      S(2) => RNG_n_69,
      S(1) => RNG_n_70,
      S(0) => RNG_n_71
    );
\addra_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => addra_carry_n_0,
      CO(3) => \addra_carry__0_n_0\,
      CO(2) => \addra_carry__0_n_1\,
      CO(1) => \addra_carry__0_n_2\,
      CO(0) => \addra_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => OP3(7 downto 4),
      O(3 downto 0) => addra(7 downto 4),
      S(3) => RNG_n_72,
      S(2) => RNG_n_73,
      S(1) => RNG_n_74,
      S(0) => RNG_n_75
    );
\addra_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \addra_carry__0_n_0\,
      CO(3 downto 1) => \NLW_addra_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \addra_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => OP3(8),
      O(3 downto 2) => \NLW_addra_carry__1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => addra(9 downto 8),
      S(3 downto 2) => B"00",
      S(1) => RNG_n_66,
      S(0) => RNG_n_67
    );
addrb_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => addrb_carry_n_0,
      CO(2) => addrb_carry_n_1,
      CO(1) => addrb_carry_n_2,
      CO(0) => addrb_carry_n_3,
      CYINIT => '0',
      DI(3 downto 0) => OP1_or_OP2(3 downto 0),
      O(3 downto 0) => addrb(3 downto 0),
      S(3) => addrb_carry_i_1_n_0,
      S(2) => addrb_carry_i_2_n_0,
      S(1) => addrb_carry_i_3_n_0,
      S(0) => addrb_carry_i_4_n_0
    );
\addrb_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => addrb_carry_n_0,
      CO(3) => \addrb_carry__0_n_0\,
      CO(2) => \addrb_carry__0_n_1\,
      CO(1) => \addrb_carry__0_n_2\,
      CO(0) => \addrb_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => OP1_or_OP2(7 downto 4),
      O(3 downto 0) => addrb(7 downto 4),
      S(3) => \addrb_carry__0_i_1_n_0\,
      S(2) => \addrb_carry__0_i_2_n_0\,
      S(1) => \addrb_carry__0_i_3_n_0\,
      S(0) => \addrb_carry__0_i_4_n_0\
    );
\addrb_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(7),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(7),
      O => \addrb_carry__0_i_1_n_0\
    );
\addrb_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(6),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(6),
      O => \addrb_carry__0_i_2_n_0\
    );
\addrb_carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(5),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(5),
      O => \addrb_carry__0_i_3_n_0\
    );
\addrb_carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(4),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(4),
      O => \addrb_carry__0_i_4_n_0\
    );
\addrb_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \addrb_carry__0_n_0\,
      CO(3 downto 1) => \NLW_addrb_carry__1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \addrb_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 1) => B"000",
      DI(0) => OP1_or_OP2(8),
      O(3 downto 2) => \NLW_addrb_carry__1_O_UNCONNECTED\(3 downto 2),
      O(1 downto 0) => addrb(9 downto 8),
      S(3 downto 2) => B"00",
      S(1) => \addrb_carry__1_i_1_n_0\,
      S(0) => \addrb_carry__1_i_2_n_0\
    );
\addrb_carry__1_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(9),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(9),
      O => \addrb_carry__1_i_1_n_0\
    );
\addrb_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(8),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(8),
      O => \addrb_carry__1_i_2_n_0\
    );
addrb_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(3),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(3),
      O => addrb_carry_i_1_n_0
    );
addrb_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(2),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(2),
      O => addrb_carry_i_2_n_0
    );
addrb_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(1),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(1),
      O => addrb_carry_i_3_n_0
    );
addrb_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55556555AAAAAAAA"
    )
        port map (
      I0 => OP1_or_OP2(0),
      I1 => \command_reg0_reg_n_0_[3]\,
      I2 => \command_reg0_reg_n_0_[4]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      I5 => control_low_word(0),
      O => addrb_carry_i_4_n_0
    );
\command_reg0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(0),
      Q => \command_reg0_reg_n_0_[0]\,
      R => control_high_word(0)
    );
\command_reg0_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(10),
      Q => OP1_or_OP2(5),
      R => control_high_word(0)
    );
\command_reg0_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(11),
      Q => OP1_or_OP2(6),
      R => control_high_word(0)
    );
\command_reg0_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(12),
      Q => OP1_or_OP2(7),
      R => control_high_word(0)
    );
\command_reg0_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(13),
      Q => OP1_or_OP2(8),
      R => control_high_word(0)
    );
\command_reg0_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(14),
      Q => OP1_or_OP2(9),
      R => control_high_word(0)
    );
\command_reg0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(1),
      Q => \command_reg0_reg_n_0_[1]\,
      R => control_high_word(0)
    );
\command_reg0_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(15),
      Q => OP3(0),
      R => control_high_word(0)
    );
\command_reg0_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(16),
      Q => OP3(1),
      R => control_high_word(0)
    );
\command_reg0_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(17),
      Q => OP3(2),
      R => control_high_word(0)
    );
\command_reg0_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(18),
      Q => OP3(3),
      R => control_high_word(0)
    );
\command_reg0_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(19),
      Q => OP3(4),
      R => control_high_word(0)
    );
\command_reg0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(2),
      Q => \command_reg0_reg_n_0_[2]\,
      R => control_high_word(0)
    );
\command_reg0_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(20),
      Q => OP3(5),
      R => control_high_word(0)
    );
\command_reg0_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(21),
      Q => OP3(6),
      R => control_high_word(0)
    );
\command_reg0_reg[32]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(22),
      Q => OP3(7),
      R => control_high_word(0)
    );
\command_reg0_reg[33]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(23),
      Q => OP3(8),
      R => control_high_word(0)
    );
\command_reg0_reg[34]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(24),
      Q => OP3(9),
      R => control_high_word(0)
    );
\command_reg0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(3),
      Q => \command_reg0_reg_n_0_[3]\,
      R => control_high_word(0)
    );
\command_reg0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(4),
      Q => \command_reg0_reg_n_0_[4]\,
      R => control_high_word(0)
    );
\command_reg0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(5),
      Q => OP1_or_OP2(0),
      R => control_high_word(0)
    );
\command_reg0_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(6),
      Q => OP1_or_OP2(1),
      R => control_high_word(0)
    );
\command_reg0_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(7),
      Q => OP1_or_OP2(2),
      R => control_high_word(0)
    );
\command_reg0_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(8),
      Q => OP1_or_OP2(3),
      R => control_high_word(0)
    );
\command_reg0_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => qdpo(25),
      D => qdpo(9),
      Q => OP1_or_OP2(4),
      R => control_high_word(0)
    );
error_trng_reg_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => \command_reg0_reg_n_0_[3]\,
      I1 => \command_reg0_reg_n_0_[4]\,
      I2 => \command_reg0_reg_n_0_[0]\,
      I3 => \command_reg0_reg_n_0_[1]\,
      I4 => \command_reg0_reg_n_0_[2]\,
      O => error_trng_reg_i_2_n_0
    );
error_trng_reg_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => RNG_n_76,
      Q => \^d_1\(0),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper is
  port (
    clk : in STD_LOGIC;
    control_low_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    control_high_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dina_ext_low_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dina_ext_high_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dout_ext_low_word : out STD_LOGIC_VECTOR ( 31 downto 0 );
    dout_ext_high_word : out STD_LOGIC_VECTOR ( 31 downto 0 );
    status : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper : entity is "ComputeCoreWrapper";
end cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper is
  signal CORE_n_65 : STD_LOGIC;
  signal command_in : STD_LOGIC_VECTOR ( 34 downto 0 );
  signal command_we0 : STD_LOGIC;
  signal cycle_count_reg : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal done_all_computation : STD_LOGIC;
  signal error_trng_reg : STD_LOGIC;
begin
CORE: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore
     port map (
      D(0) => error_trng_reg,
      clk => clk,
      \command_reg0_reg[0]_0\ => CORE_n_65,
      control_high_word(0) => control_high_word(0),
      control_low_word(11 downto 0) => control_low_word(11 downto 0),
      \^d\(36 downto 32) => dina_ext_high_word(4 downto 0),
      \^d\(31 downto 0) => dina_ext_low_word(31 downto 0),
      dina_ext_high_word(26 downto 0) => dina_ext_high_word(31 downto 5),
      doutb(63 downto 32) => dout_ext_high_word(31 downto 0),
      doutb(31 downto 0) => dout_ext_low_word(31 downto 0),
      qdpo(25) => command_we0,
      qdpo(24 downto 15) => command_in(34 downto 25),
      qdpo(14 downto 0) => command_in(14 downto 0)
    );
ISA_CTRL: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control
     port map (
      D(30 downto 1) => cycle_count_reg(29 downto 0),
      D(0) => done_all_computation,
      \FSM_sequential_state_reg[1]_0\ => CORE_n_65,
      clk => clk,
      control_high_word(1 downto 0) => control_high_word(1 downto 0),
      control_low_word(7 downto 6) => control_low_word(11 downto 10),
      control_low_word(5 downto 0) => control_low_word(5 downto 0),
      \^d\(36 downto 32) => dina_ext_high_word(4 downto 0),
      \^d\(31 downto 0) => dina_ext_low_word(31 downto 0),
      qdpo(25) => command_we0,
      qdpo(24 downto 15) => command_in(34 downto 25),
      qdpo(14 downto 0) => command_in(14 downto 0)
    );
\status_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => done_all_computation,
      Q => status(0),
      R => '0'
    );
\status_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(8),
      Q => status(10),
      R => '0'
    );
\status_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(9),
      Q => status(11),
      R => '0'
    );
\status_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(10),
      Q => status(12),
      R => '0'
    );
\status_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(11),
      Q => status(13),
      R => '0'
    );
\status_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(12),
      Q => status(14),
      R => '0'
    );
\status_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(13),
      Q => status(15),
      R => '0'
    );
\status_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(14),
      Q => status(16),
      R => '0'
    );
\status_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(15),
      Q => status(17),
      R => '0'
    );
\status_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(16),
      Q => status(18),
      R => '0'
    );
\status_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(17),
      Q => status(19),
      R => '0'
    );
\status_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => error_trng_reg,
      Q => status(1),
      R => '0'
    );
\status_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(18),
      Q => status(20),
      R => '0'
    );
\status_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(19),
      Q => status(21),
      R => '0'
    );
\status_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(20),
      Q => status(22),
      R => '0'
    );
\status_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(21),
      Q => status(23),
      R => '0'
    );
\status_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(22),
      Q => status(24),
      R => '0'
    );
\status_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(23),
      Q => status(25),
      R => '0'
    );
\status_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(24),
      Q => status(26),
      R => '0'
    );
\status_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(25),
      Q => status(27),
      R => '0'
    );
\status_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(26),
      Q => status(28),
      R => '0'
    );
\status_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(27),
      Q => status(29),
      R => '0'
    );
\status_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(0),
      Q => status(2),
      R => '0'
    );
\status_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(28),
      Q => status(30),
      R => '0'
    );
\status_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(29),
      Q => status(31),
      R => '0'
    );
\status_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(1),
      Q => status(3),
      R => '0'
    );
\status_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(2),
      Q => status(4),
      R => '0'
    );
\status_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(3),
      Q => status(5),
      R => '0'
    );
\status_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(4),
      Q => status(6),
      R => '0'
    );
\status_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(5),
      Q => status(7),
      R => '0'
    );
\status_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(6),
      Q => status(8),
      R => '0'
    );
\status_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => cycle_count_reg(7),
      Q => status(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cryptoprocessor_ComputeCoreWrapper_0_0 is
  port (
    clk : in STD_LOGIC;
    control_low_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    control_high_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dina_ext_low_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dina_ext_high_word : in STD_LOGIC_VECTOR ( 31 downto 0 );
    dout_ext_low_word : out STD_LOGIC_VECTOR ( 31 downto 0 );
    dout_ext_high_word : out STD_LOGIC_VECTOR ( 31 downto 0 );
    status : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of cryptoprocessor_ComputeCoreWrapper_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of cryptoprocessor_ComputeCoreWrapper_0_0 : entity is "cryptoprocessor_ComputeCoreWrapper_0_0,ComputeCoreWrapper,{}";
  attribute DowngradeIPIdentifiedWarnings : string;
  attribute DowngradeIPIdentifiedWarnings of cryptoprocessor_ComputeCoreWrapper_0_0 : entity is "yes";
  attribute IP_DEFINITION_SOURCE : string;
  attribute IP_DEFINITION_SOURCE of cryptoprocessor_ComputeCoreWrapper_0_0 : entity is "module_ref";
  attribute X_CORE_INFO : string;
  attribute X_CORE_INFO of cryptoprocessor_ComputeCoreWrapper_0_0 : entity is "ComputeCoreWrapper,Vivado 2020.2";
end cryptoprocessor_ComputeCoreWrapper_0_0;

architecture STRUCTURE of cryptoprocessor_ComputeCoreWrapper_0_0 is
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cryptoprocessor_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0";
begin
inst: entity work.cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper
     port map (
      clk => clk,
      control_high_word(31 downto 2) => B"000000000000000000000000000000",
      control_high_word(1 downto 0) => control_high_word(1 downto 0),
      control_low_word(31 downto 12) => B"00000000000000000000",
      control_low_word(11 downto 0) => control_low_word(11 downto 0),
      dina_ext_high_word(31 downto 0) => dina_ext_high_word(31 downto 0),
      dina_ext_low_word(31 downto 0) => dina_ext_low_word(31 downto 0),
      dout_ext_high_word(31 downto 0) => dout_ext_high_word(31 downto 0),
      dout_ext_low_word(31 downto 0) => dout_ext_low_word(31 downto 0),
      status(31 downto 0) => status(31 downto 0)
    );
end STRUCTURE;
