// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2020.2 (lin64) Build 3064766 Wed Nov 18 09:12:47 MST 2020
// Date        : Wed Dec 20 12:17:39 2023
// Host        : t460sacm running 64-bit Ubuntu 20.04.6 LTS
// Command     : write_verilog -force -mode funcsim
//               /home/amert/Documents/Classes/Class-CryptEng-W2023/assignments/2/Sujoys_code/Assignment2/CryptoProcessor/CryptoProcessor_2022_23/project_1/project_1.srcs/sources_1/bd/cryptoprocessor/ip/cryptoprocessor_ComputeCoreWrapper_0_0/cryptoprocessor_ComputeCoreWrapper_0_0_sim_netlist.v
// Design      : cryptoprocessor_ComputeCoreWrapper_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7z020clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "cryptoprocessor_ComputeCoreWrapper_0_0,ComputeCoreWrapper,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* IP_DEFINITION_SOURCE = "module_ref" *) 
(* X_CORE_INFO = "ComputeCoreWrapper,Vivado 2020.2" *) 
(* NotValidForBitStream *)
module cryptoprocessor_ComputeCoreWrapper_0_0
   (clk,
    control_low_word,
    control_high_word,
    dina_ext_low_word,
    dina_ext_high_word,
    dout_ext_low_word,
    dout_ext_high_word,
    status);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, CLK_DOMAIN cryptoprocessor_processing_system7_0_0_FCLK_CLK0, INSERT_VIP 0" *) input clk;
  input [31:0]control_low_word;
  input [31:0]control_high_word;
  input [31:0]dina_ext_low_word;
  input [31:0]dina_ext_high_word;
  output [31:0]dout_ext_low_word;
  output [31:0]dout_ext_high_word;
  output [31:0]status;

  wire clk;
  wire [31:0]control_high_word;
  wire [31:0]control_low_word;
  wire [31:0]dina_ext_high_word;
  wire [31:0]dina_ext_low_word;
  wire [31:0]dout_ext_high_word;
  wire [31:0]dout_ext_low_word;
  wire [31:0]status;

  cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper inst
       (.clk(clk),
        .control_high_word({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,control_high_word[1:0]}),
        .control_low_word({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,control_low_word[11:0]}),
        .dina_ext_high_word(dina_ext_high_word),
        .dina_ext_low_word(dina_ext_low_word),
        .dout_ext_high_word(dout_ext_high_word),
        .dout_ext_low_word(dout_ext_low_word),
        .status(status));
endmodule

(* CHECK_LICENSE_TYPE = "BRAM64_1024,blk_mem_gen_v8_4_4,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "BRAM64_1024" *) 
(* X_CORE_INFO = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024
   (clka,
    wea,
    addra,
    dina,
    clkb,
    addrb,
    doutb);
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [63:0]dina;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clkb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR" *) input [9:0]addrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT" *) output [63:0]doutb;

  wire [9:0]addra;
  wire [9:0]addrb;
  wire clka;
  wire [63:0]dina;
  wire [63:0]doutb;
  wire [0:0]wea;
  wire NLW_U0_dbiterr_UNCONNECTED;
  wire NLW_U0_rsta_busy_UNCONNECTED;
  wire NLW_U0_rstb_busy_UNCONNECTED;
  wire NLW_U0_s_axi_arready_UNCONNECTED;
  wire NLW_U0_s_axi_awready_UNCONNECTED;
  wire NLW_U0_s_axi_bvalid_UNCONNECTED;
  wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_rlast_UNCONNECTED;
  wire NLW_U0_s_axi_rvalid_UNCONNECTED;
  wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
  wire NLW_U0_s_axi_wready_UNCONNECTED;
  wire NLW_U0_sbiterr_UNCONNECTED;
  wire [63:0]NLW_U0_douta_UNCONNECTED;
  wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
  wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
  wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
  wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
  wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;

  (* C_ADDRA_WIDTH = "10" *) 
  (* C_ADDRB_WIDTH = "10" *) 
  (* C_ALGORITHM = "1" *) 
  (* C_AXI_ID_WIDTH = "4" *) 
  (* C_AXI_SLAVE_TYPE = "0" *) 
  (* C_AXI_TYPE = "1" *) 
  (* C_BYTE_SIZE = "9" *) 
  (* C_COMMON_CLK = "1" *) 
  (* C_COUNT_18K_BRAM = "0" *) 
  (* C_COUNT_36K_BRAM = "2" *) 
  (* C_CTRL_ECC_ALGO = "NONE" *) 
  (* C_DEFAULT_DATA = "0" *) 
  (* C_DISABLE_WARN_BHV_COLL = "0" *) 
  (* C_DISABLE_WARN_BHV_RANGE = "0" *) 
  (* C_ELABORATION_DIR = "./" *) 
  (* C_ENABLE_32BIT_ADDRESS = "0" *) 
  (* C_EN_DEEPSLEEP_PIN = "0" *) 
  (* C_EN_ECC_PIPE = "0" *) 
  (* C_EN_RDADDRA_CHG = "0" *) 
  (* C_EN_RDADDRB_CHG = "0" *) 
  (* C_EN_SAFETY_CKT = "0" *) 
  (* C_EN_SHUTDOWN_PIN = "0" *) 
  (* C_EN_SLEEP_PIN = "0" *) 
  (* C_EST_POWER_SUMMARY = "Estimated Power for IP     :     10.882749 mW" *) 
  (* C_FAMILY = "zynq" *) 
  (* C_HAS_AXI_ID = "0" *) 
  (* C_HAS_ENA = "0" *) 
  (* C_HAS_ENB = "0" *) 
  (* C_HAS_INJECTERR = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MEM_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) 
  (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) 
  (* C_HAS_REGCEA = "0" *) 
  (* C_HAS_REGCEB = "0" *) 
  (* C_HAS_RSTA = "0" *) 
  (* C_HAS_RSTB = "0" *) 
  (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) 
  (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) 
  (* C_INITA_VAL = "0" *) 
  (* C_INITB_VAL = "0" *) 
  (* C_INIT_FILE = "BRAM64_1024.mem" *) 
  (* C_INIT_FILE_NAME = "no_coe_file_loaded" *) 
  (* C_INTERFACE_TYPE = "0" *) 
  (* C_LOAD_INIT_FILE = "0" *) 
  (* C_MEM_TYPE = "1" *) 
  (* C_MUX_PIPELINE_STAGES = "0" *) 
  (* C_PRIM_TYPE = "1" *) 
  (* C_READ_DEPTH_A = "1024" *) 
  (* C_READ_DEPTH_B = "1024" *) 
  (* C_READ_LATENCY_A = "1" *) 
  (* C_READ_LATENCY_B = "1" *) 
  (* C_READ_WIDTH_A = "64" *) 
  (* C_READ_WIDTH_B = "64" *) 
  (* C_RSTRAM_A = "0" *) 
  (* C_RSTRAM_B = "0" *) 
  (* C_RST_PRIORITY_A = "CE" *) 
  (* C_RST_PRIORITY_B = "CE" *) 
  (* C_SIM_COLLISION_CHECK = "ALL" *) 
  (* C_USE_BRAM_BLOCK = "0" *) 
  (* C_USE_BYTE_WEA = "0" *) 
  (* C_USE_BYTE_WEB = "0" *) 
  (* C_USE_DEFAULT_DATA = "0" *) 
  (* C_USE_ECC = "0" *) 
  (* C_USE_SOFTECC = "0" *) 
  (* C_USE_URAM = "0" *) 
  (* C_WEA_WIDTH = "1" *) 
  (* C_WEB_WIDTH = "1" *) 
  (* C_WRITE_DEPTH_A = "1024" *) 
  (* C_WRITE_DEPTH_B = "1024" *) 
  (* C_WRITE_MODE_A = "NO_CHANGE" *) 
  (* C_WRITE_MODE_B = "READ_FIRST" *) 
  (* C_WRITE_WIDTH_A = "64" *) 
  (* C_WRITE_WIDTH_B = "64" *) 
  (* C_XDEVICEFAMILY = "zynq" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  (* is_du_within_envelope = "true" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_blk_mem_gen_v8_4_4 U0
       (.addra(addra),
        .addrb(addrb),
        .clka(clka),
        .clkb(1'b0),
        .dbiterr(NLW_U0_dbiterr_UNCONNECTED),
        .deepsleep(1'b0),
        .dina(dina),
        .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .douta(NLW_U0_douta_UNCONNECTED[63:0]),
        .doutb(doutb),
        .eccpipece(1'b0),
        .ena(1'b0),
        .enb(1'b0),
        .injectdbiterr(1'b0),
        .injectsbiterr(1'b0),
        .rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
        .regcea(1'b0),
        .regceb(1'b0),
        .rsta(1'b0),
        .rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
        .rstb(1'b0),
        .rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
        .s_aclk(1'b0),
        .s_aresetn(1'b0),
        .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arburst({1'b0,1'b0}),
        .s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
        .s_axi_arsize({1'b0,1'b0,1'b0}),
        .s_axi_arvalid(1'b0),
        .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awburst({1'b0,1'b0}),
        .s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
        .s_axi_awsize({1'b0,1'b0,1'b0}),
        .s_axi_awvalid(1'b0),
        .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
        .s_axi_bready(1'b0),
        .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
        .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
        .s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
        .s_axi_injectdbiterr(1'b0),
        .s_axi_injectsbiterr(1'b0),
        .s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
        .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
        .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
        .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
        .s_axi_rready(1'b0),
        .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
        .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
        .s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
        .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .s_axi_wlast(1'b0),
        .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
        .s_axi_wstrb(1'b0),
        .s_axi_wvalid(1'b0),
        .sbiterr(NLW_U0_sbiterr_UNCONNECTED),
        .shutdown(1'b0),
        .sleep(1'b0),
        .wea(wea),
        .web(1'b0));
endmodule

(* ORIG_REF_NAME = "ComputeCore" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore
   (doutb,
    D,
    \command_reg0_reg[0]_0 ,
    clk,
    d,
    dina_ext_high_word,
    control_low_word,
    control_high_word,
    qdpo);
  output [63:0]doutb;
  output [0:0]D;
  output \command_reg0_reg[0]_0 ;
  input clk;
  input [36:0]d;
  input [26:0]dina_ext_high_word;
  input [11:0]control_low_word;
  input [0:0]control_high_word;
  input [25:0]qdpo;

  wire [0:0]D;
  wire [9:0]OP1_or_OP2;
  wire [9:0]OP3;
  wire RNG_n_66;
  wire RNG_n_67;
  wire RNG_n_68;
  wire RNG_n_69;
  wire RNG_n_70;
  wire RNG_n_71;
  wire RNG_n_72;
  wire RNG_n_73;
  wire RNG_n_74;
  wire RNG_n_75;
  wire RNG_n_76;
  wire [9:0]addra;
  wire addra_carry__0_n_0;
  wire addra_carry__0_n_1;
  wire addra_carry__0_n_2;
  wire addra_carry__0_n_3;
  wire addra_carry__1_n_3;
  wire addra_carry_n_0;
  wire addra_carry_n_1;
  wire addra_carry_n_2;
  wire addra_carry_n_3;
  wire [9:0]addrb;
  wire addrb_carry__0_i_1_n_0;
  wire addrb_carry__0_i_2_n_0;
  wire addrb_carry__0_i_3_n_0;
  wire addrb_carry__0_i_4_n_0;
  wire addrb_carry__0_n_0;
  wire addrb_carry__0_n_1;
  wire addrb_carry__0_n_2;
  wire addrb_carry__0_n_3;
  wire addrb_carry__1_i_1_n_0;
  wire addrb_carry__1_i_2_n_0;
  wire addrb_carry__1_n_3;
  wire addrb_carry_i_1_n_0;
  wire addrb_carry_i_2_n_0;
  wire addrb_carry_i_3_n_0;
  wire addrb_carry_i_4_n_0;
  wire addrb_carry_n_0;
  wire addrb_carry_n_1;
  wire addrb_carry_n_2;
  wire addrb_carry_n_3;
  wire clk;
  wire \command_reg0_reg[0]_0 ;
  wire \command_reg0_reg_n_0_[0] ;
  wire \command_reg0_reg_n_0_[1] ;
  wire \command_reg0_reg_n_0_[2] ;
  wire \command_reg0_reg_n_0_[3] ;
  wire \command_reg0_reg_n_0_[4] ;
  wire [0:0]control_high_word;
  wire [11:0]control_low_word;
  wire [36:0]d;
  wire [63:0]dina;
  wire [26:0]dina_ext_high_word;
  wire [63:0]doutb;
  wire error_trng_reg_i_2_n_0;
  wire [25:0]qdpo;
  wire wea;
  wire [3:1]NLW_addra_carry__1_CO_UNCONNECTED;
  wire [3:2]NLW_addra_carry__1_O_UNCONNECTED;
  wire [3:1]NLW_addrb_carry__1_CO_UNCONNECTED;
  wire [3:2]NLW_addrb_carry__1_O_UNCONNECTED;

  (* CHECK_LICENSE_TYPE = "BRAM64_1024,blk_mem_gen_v8_4_4,{}" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2020.2" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_BRAM64_1024 BR
       (.addra(addra),
        .addrb(addrb),
        .clka(clk),
        .clkb(1'b0),
        .dina(dina),
        .doutb(doutb),
        .wea(wea));
  cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper RNG
       (.D(D),
        .Q({OP3,OP1_or_OP2,\command_reg0_reg_n_0_[4] ,\command_reg0_reg_n_0_[3] ,\command_reg0_reg_n_0_[2] ,\command_reg0_reg_n_0_[1] ,\command_reg0_reg_n_0_[0] }),
        .S({RNG_n_66,RNG_n_67}),
        .clk(clk),
        .\command_reg0_reg[0] (\command_reg0_reg[0]_0 ),
        .\command_reg0_reg[28] ({RNG_n_68,RNG_n_69,RNG_n_70,RNG_n_71}),
        .\command_reg0_reg[32] ({RNG_n_72,RNG_n_73,RNG_n_74,RNG_n_75}),
        .control_low_word(control_low_word),
        .d(d),
        .dina(dina),
        .dina_ext_high_word(dina_ext_high_word),
        .error_reg_0(RNG_n_76),
        .error_trng_reg_reg(error_trng_reg_i_2_n_0),
        .wea(wea));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addra_carry
       (.CI(1'b0),
        .CO({addra_carry_n_0,addra_carry_n_1,addra_carry_n_2,addra_carry_n_3}),
        .CYINIT(1'b0),
        .DI(OP3[3:0]),
        .O(addra[3:0]),
        .S({RNG_n_68,RNG_n_69,RNG_n_70,RNG_n_71}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addra_carry__0
       (.CI(addra_carry_n_0),
        .CO({addra_carry__0_n_0,addra_carry__0_n_1,addra_carry__0_n_2,addra_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI(OP3[7:4]),
        .O(addra[7:4]),
        .S({RNG_n_72,RNG_n_73,RNG_n_74,RNG_n_75}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addra_carry__1
       (.CI(addra_carry__0_n_0),
        .CO({NLW_addra_carry__1_CO_UNCONNECTED[3:1],addra_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,OP3[8]}),
        .O({NLW_addra_carry__1_O_UNCONNECTED[3:2],addra[9:8]}),
        .S({1'b0,1'b0,RNG_n_66,RNG_n_67}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addrb_carry
       (.CI(1'b0),
        .CO({addrb_carry_n_0,addrb_carry_n_1,addrb_carry_n_2,addrb_carry_n_3}),
        .CYINIT(1'b0),
        .DI(OP1_or_OP2[3:0]),
        .O(addrb[3:0]),
        .S({addrb_carry_i_1_n_0,addrb_carry_i_2_n_0,addrb_carry_i_3_n_0,addrb_carry_i_4_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addrb_carry__0
       (.CI(addrb_carry_n_0),
        .CO({addrb_carry__0_n_0,addrb_carry__0_n_1,addrb_carry__0_n_2,addrb_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI(OP1_or_OP2[7:4]),
        .O(addrb[7:4]),
        .S({addrb_carry__0_i_1_n_0,addrb_carry__0_i_2_n_0,addrb_carry__0_i_3_n_0,addrb_carry__0_i_4_n_0}));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__0_i_1
       (.I0(OP1_or_OP2[7]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[7]),
        .O(addrb_carry__0_i_1_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__0_i_2
       (.I0(OP1_or_OP2[6]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[6]),
        .O(addrb_carry__0_i_2_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__0_i_3
       (.I0(OP1_or_OP2[5]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[5]),
        .O(addrb_carry__0_i_3_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__0_i_4
       (.I0(OP1_or_OP2[4]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[4]),
        .O(addrb_carry__0_i_4_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 addrb_carry__1
       (.CI(addrb_carry__0_n_0),
        .CO({NLW_addrb_carry__1_CO_UNCONNECTED[3:1],addrb_carry__1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,OP1_or_OP2[8]}),
        .O({NLW_addrb_carry__1_O_UNCONNECTED[3:2],addrb[9:8]}),
        .S({1'b0,1'b0,addrb_carry__1_i_1_n_0,addrb_carry__1_i_2_n_0}));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__1_i_1
       (.I0(OP1_or_OP2[9]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[9]),
        .O(addrb_carry__1_i_1_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry__1_i_2
       (.I0(OP1_or_OP2[8]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[8]),
        .O(addrb_carry__1_i_2_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry_i_1
       (.I0(OP1_or_OP2[3]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[3]),
        .O(addrb_carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry_i_2
       (.I0(OP1_or_OP2[2]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[2]),
        .O(addrb_carry_i_2_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry_i_3
       (.I0(OP1_or_OP2[1]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[1]),
        .O(addrb_carry_i_3_n_0));
  LUT6 #(
    .INIT(64'h55556555AAAAAAAA)) 
    addrb_carry_i_4
       (.I0(OP1_or_OP2[0]),
        .I1(\command_reg0_reg_n_0_[3] ),
        .I2(\command_reg0_reg_n_0_[4] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .I5(control_low_word[0]),
        .O(addrb_carry_i_4_n_0));
  FDRE \command_reg0_reg[0] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[0]),
        .Q(\command_reg0_reg_n_0_[0] ),
        .R(control_high_word));
  FDRE \command_reg0_reg[10] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[10]),
        .Q(OP1_or_OP2[5]),
        .R(control_high_word));
  FDRE \command_reg0_reg[11] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[11]),
        .Q(OP1_or_OP2[6]),
        .R(control_high_word));
  FDRE \command_reg0_reg[12] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[12]),
        .Q(OP1_or_OP2[7]),
        .R(control_high_word));
  FDRE \command_reg0_reg[13] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[13]),
        .Q(OP1_or_OP2[8]),
        .R(control_high_word));
  FDRE \command_reg0_reg[14] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[14]),
        .Q(OP1_or_OP2[9]),
        .R(control_high_word));
  FDRE \command_reg0_reg[1] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[1]),
        .Q(\command_reg0_reg_n_0_[1] ),
        .R(control_high_word));
  FDRE \command_reg0_reg[25] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[15]),
        .Q(OP3[0]),
        .R(control_high_word));
  FDRE \command_reg0_reg[26] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[16]),
        .Q(OP3[1]),
        .R(control_high_word));
  FDRE \command_reg0_reg[27] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[17]),
        .Q(OP3[2]),
        .R(control_high_word));
  FDRE \command_reg0_reg[28] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[18]),
        .Q(OP3[3]),
        .R(control_high_word));
  FDRE \command_reg0_reg[29] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[19]),
        .Q(OP3[4]),
        .R(control_high_word));
  FDRE \command_reg0_reg[2] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[2]),
        .Q(\command_reg0_reg_n_0_[2] ),
        .R(control_high_word));
  FDRE \command_reg0_reg[30] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[20]),
        .Q(OP3[5]),
        .R(control_high_word));
  FDRE \command_reg0_reg[31] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[21]),
        .Q(OP3[6]),
        .R(control_high_word));
  FDRE \command_reg0_reg[32] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[22]),
        .Q(OP3[7]),
        .R(control_high_word));
  FDRE \command_reg0_reg[33] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[23]),
        .Q(OP3[8]),
        .R(control_high_word));
  FDRE \command_reg0_reg[34] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[24]),
        .Q(OP3[9]),
        .R(control_high_word));
  FDRE \command_reg0_reg[3] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[3]),
        .Q(\command_reg0_reg_n_0_[3] ),
        .R(control_high_word));
  FDRE \command_reg0_reg[4] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[4]),
        .Q(\command_reg0_reg_n_0_[4] ),
        .R(control_high_word));
  FDRE \command_reg0_reg[5] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[5]),
        .Q(OP1_or_OP2[0]),
        .R(control_high_word));
  FDRE \command_reg0_reg[6] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[6]),
        .Q(OP1_or_OP2[1]),
        .R(control_high_word));
  FDRE \command_reg0_reg[7] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[7]),
        .Q(OP1_or_OP2[2]),
        .R(control_high_word));
  FDRE \command_reg0_reg[8] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[8]),
        .Q(OP1_or_OP2[3]),
        .R(control_high_word));
  FDRE \command_reg0_reg[9] 
       (.C(clk),
        .CE(qdpo[25]),
        .D(qdpo[9]),
        .Q(OP1_or_OP2[4]),
        .R(control_high_word));
  LUT5 #(
    .INIT(32'h00040000)) 
    error_trng_reg_i_2
       (.I0(\command_reg0_reg_n_0_[3] ),
        .I1(\command_reg0_reg_n_0_[4] ),
        .I2(\command_reg0_reg_n_0_[0] ),
        .I3(\command_reg0_reg_n_0_[1] ),
        .I4(\command_reg0_reg_n_0_[2] ),
        .O(error_trng_reg_i_2_n_0));
  FDRE error_trng_reg_reg
       (.C(clk),
        .CE(1'b1),
        .D(RNG_n_76),
        .Q(D),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "ComputeCoreWrapper" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCoreWrapper
   (clk,
    control_low_word,
    control_high_word,
    dina_ext_low_word,
    dina_ext_high_word,
    dout_ext_low_word,
    dout_ext_high_word,
    status);
  input clk;
  input [31:0]control_low_word;
  input [31:0]control_high_word;
  input [31:0]dina_ext_low_word;
  input [31:0]dina_ext_high_word;
  output [31:0]dout_ext_low_word;
  output [31:0]dout_ext_high_word;
  output [31:0]status;

  wire CORE_n_65;
  wire clk;
  wire [34:0]command_in;
  wire command_we0;
  wire [31:0]control_high_word;
  wire [31:0]control_low_word;
  wire [29:0]cycle_count_reg;
  wire [31:0]dina_ext_high_word;
  wire [31:0]dina_ext_low_word;
  wire done_all_computation;
  wire [31:0]dout_ext_high_word;
  wire [31:0]dout_ext_low_word;
  wire error_trng_reg;
  wire [31:0]status;

  cryptoprocessor_ComputeCoreWrapper_0_0_ComputeCore CORE
       (.D(error_trng_reg),
        .clk(clk),
        .\command_reg0_reg[0]_0 (CORE_n_65),
        .control_high_word(control_high_word[0]),
        .control_low_word(control_low_word[11:0]),
        .d({dina_ext_high_word[4:0],dina_ext_low_word}),
        .dina_ext_high_word(dina_ext_high_word[31:5]),
        .doutb({dout_ext_high_word,dout_ext_low_word}),
        .qdpo({command_we0,command_in[34:25],command_in[14:0]}));
  cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control ISA_CTRL
       (.D({cycle_count_reg,done_all_computation}),
        .\FSM_sequential_state_reg[1]_0 (CORE_n_65),
        .clk(clk),
        .control_high_word(control_high_word[1:0]),
        .control_low_word({control_low_word[11:10],control_low_word[5:0]}),
        .d({dina_ext_high_word[4:0],dina_ext_low_word}),
        .qdpo({command_we0,command_in[34:25],command_in[14:0]}));
  FDRE \status_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(done_all_computation),
        .Q(status[0]),
        .R(1'b0));
  FDRE \status_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[8]),
        .Q(status[10]),
        .R(1'b0));
  FDRE \status_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[9]),
        .Q(status[11]),
        .R(1'b0));
  FDRE \status_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[10]),
        .Q(status[12]),
        .R(1'b0));
  FDRE \status_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[11]),
        .Q(status[13]),
        .R(1'b0));
  FDRE \status_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[12]),
        .Q(status[14]),
        .R(1'b0));
  FDRE \status_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[13]),
        .Q(status[15]),
        .R(1'b0));
  FDRE \status_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[14]),
        .Q(status[16]),
        .R(1'b0));
  FDRE \status_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[15]),
        .Q(status[17]),
        .R(1'b0));
  FDRE \status_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[16]),
        .Q(status[18]),
        .R(1'b0));
  FDRE \status_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[17]),
        .Q(status[19]),
        .R(1'b0));
  FDRE \status_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(error_trng_reg),
        .Q(status[1]),
        .R(1'b0));
  FDRE \status_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[18]),
        .Q(status[20]),
        .R(1'b0));
  FDRE \status_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[19]),
        .Q(status[21]),
        .R(1'b0));
  FDRE \status_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[20]),
        .Q(status[22]),
        .R(1'b0));
  FDRE \status_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[21]),
        .Q(status[23]),
        .R(1'b0));
  FDRE \status_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[22]),
        .Q(status[24]),
        .R(1'b0));
  FDRE \status_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[23]),
        .Q(status[25]),
        .R(1'b0));
  FDRE \status_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[24]),
        .Q(status[26]),
        .R(1'b0));
  FDRE \status_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[25]),
        .Q(status[27]),
        .R(1'b0));
  FDRE \status_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[26]),
        .Q(status[28]),
        .R(1'b0));
  FDRE \status_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[27]),
        .Q(status[29]),
        .R(1'b0));
  FDRE \status_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[0]),
        .Q(status[2]),
        .R(1'b0));
  FDRE \status_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[28]),
        .Q(status[30]),
        .R(1'b0));
  FDRE \status_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[29]),
        .Q(status[31]),
        .R(1'b0));
  FDRE \status_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[1]),
        .Q(status[3]),
        .R(1'b0));
  FDRE \status_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[2]),
        .Q(status[4]),
        .R(1'b0));
  FDRE \status_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[3]),
        .Q(status[5]),
        .R(1'b0));
  FDRE \status_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[4]),
        .Q(status[6]),
        .R(1'b0));
  FDRE \status_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[5]),
        .Q(status[7]),
        .R(1'b0));
  FDRE \status_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[6]),
        .Q(status[8]),
        .R(1'b0));
  FDRE \status_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(cycle_count_reg[7]),
        .Q(status[9]),
        .R(1'b0));
endmodule

(* CHECK_LICENSE_TYPE = "INS_RAM,dist_mem_gen_v8_0_13,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "INS_RAM" *) 
(* X_CORE_INFO = "dist_mem_gen_v8_0_13,Vivado 2019.1" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM
   (a,
    d,
    dpra,
    clk,
    we,
    qdpo_clk,
    qdpo);
  input [5:0]a;
  input [36:0]d;
  input [5:0]dpra;
  input clk;
  input we;
  input qdpo_clk;
  output [36:0]qdpo;

  wire \<const0> ;
  wire [5:0]a;
  wire [36:0]d;
  wire [5:0]dpra;
  wire [36:0]\^qdpo ;
  wire qdpo_clk;
  wire we;
  wire [36:0]NLW_U0_dpo_UNCONNECTED;
  wire [24:15]NLW_U0_qdpo_UNCONNECTED;
  wire [36:0]NLW_U0_qspo_UNCONNECTED;
  wire [36:0]NLW_U0_spo_UNCONNECTED;

  assign qdpo[36:25] = \^qdpo [36:25];
  assign qdpo[24] = \<const0> ;
  assign qdpo[23] = \<const0> ;
  assign qdpo[22] = \<const0> ;
  assign qdpo[21] = \<const0> ;
  assign qdpo[20] = \<const0> ;
  assign qdpo[19] = \<const0> ;
  assign qdpo[18] = \<const0> ;
  assign qdpo[17] = \<const0> ;
  assign qdpo[16] = \<const0> ;
  assign qdpo[15] = \<const0> ;
  assign qdpo[14:0] = \^qdpo [14:0];
  GND GND
       (.G(\<const0> ));
  (* C_DEFAULT_DATA = "0" *) 
  (* C_ELABORATION_DIR = "./" *) 
  (* C_FAMILY = "zynq" *) 
  (* C_HAS_CLK = "1" *) 
  (* C_HAS_D = "1" *) 
  (* C_HAS_DPO = "0" *) 
  (* C_HAS_DPRA = "1" *) 
  (* C_HAS_QDPO = "1" *) 
  (* C_HAS_QDPO_CE = "0" *) 
  (* C_HAS_QDPO_CLK = "1" *) 
  (* C_HAS_QDPO_RST = "0" *) 
  (* C_HAS_QDPO_SRST = "0" *) 
  (* C_HAS_QSPO = "0" *) 
  (* C_HAS_QSPO_RST = "0" *) 
  (* C_HAS_QSPO_SRST = "0" *) 
  (* C_HAS_SPO = "0" *) 
  (* C_HAS_WE = "1" *) 
  (* C_MEM_TYPE = "4" *) 
  (* C_REG_DPRA_INPUT = "0" *) 
  (* c_addr_width = "6" *) 
  (* c_depth = "64" *) 
  (* c_has_i_ce = "0" *) 
  (* c_has_qspo_ce = "0" *) 
  (* c_mem_init_file = "no_coe_file_loaded" *) 
  (* c_parser_type = "1" *) 
  (* c_pipeline_stages = "0" *) 
  (* c_qce_joined = "0" *) 
  (* c_qualify_we = "0" *) 
  (* c_read_mif = "0" *) 
  (* c_reg_a_d_inputs = "0" *) 
  (* c_sync_enable = "1" *) 
  (* c_width = "37" *) 
  (* is_du_within_envelope = "true" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_dist_mem_gen_v8_0_13 U0
       (.a(a),
        .clk(1'b0),
        .d(d),
        .dpo(NLW_U0_dpo_UNCONNECTED[36:0]),
        .dpra(dpra),
        .i_ce(1'b1),
        .qdpo(\^qdpo ),
        .qdpo_ce(1'b1),
        .qdpo_clk(qdpo_clk),
        .qdpo_rst(1'b0),
        .qdpo_srst(1'b0),
        .qspo(NLW_U0_qspo_UNCONNECTED[36:0]),
        .qspo_ce(1'b1),
        .qspo_rst(1'b0),
        .qspo_srst(1'b0),
        .spo(NLW_U0_spo_UNCONNECTED[36:0]),
        .we(we));
endmodule

(* ORIG_REF_NAME = "ISA_control" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_ISA_control
   (qdpo,
    D,
    control_low_word,
    d,
    clk,
    control_high_word,
    \FSM_sequential_state_reg[1]_0 );
  output [25:0]qdpo;
  output [30:0]D;
  input [7:0]control_low_word;
  input [36:0]d;
  input clk;
  input [1:0]control_high_word;
  input \FSM_sequential_state_reg[1]_0 ;

  wire [30:0]D;
  wire \FSM_sequential_state[0]_i_1_n_0 ;
  wire \FSM_sequential_state[1]_i_3_n_0 ;
  wire \FSM_sequential_state[2]_i_2_n_0 ;
  wire \FSM_sequential_state_reg[1]_0 ;
  wire IR_address0;
  wire \IR_address[5]_i_2_n_0 ;
  wire [5:0]IR_address_reg;
  wire clk;
  wire command_we1;
  wire [1:0]control_high_word;
  wire [7:0]control_low_word;
  wire \cycle_count[0]_i_2_n_0 ;
  wire \cycle_count_reg[0]_i_1_n_0 ;
  wire \cycle_count_reg[0]_i_1_n_1 ;
  wire \cycle_count_reg[0]_i_1_n_2 ;
  wire \cycle_count_reg[0]_i_1_n_3 ;
  wire \cycle_count_reg[0]_i_1_n_4 ;
  wire \cycle_count_reg[0]_i_1_n_5 ;
  wire \cycle_count_reg[0]_i_1_n_6 ;
  wire \cycle_count_reg[0]_i_1_n_7 ;
  wire \cycle_count_reg[12]_i_1_n_0 ;
  wire \cycle_count_reg[12]_i_1_n_1 ;
  wire \cycle_count_reg[12]_i_1_n_2 ;
  wire \cycle_count_reg[12]_i_1_n_3 ;
  wire \cycle_count_reg[12]_i_1_n_4 ;
  wire \cycle_count_reg[12]_i_1_n_5 ;
  wire \cycle_count_reg[12]_i_1_n_6 ;
  wire \cycle_count_reg[12]_i_1_n_7 ;
  wire \cycle_count_reg[16]_i_1_n_0 ;
  wire \cycle_count_reg[16]_i_1_n_1 ;
  wire \cycle_count_reg[16]_i_1_n_2 ;
  wire \cycle_count_reg[16]_i_1_n_3 ;
  wire \cycle_count_reg[16]_i_1_n_4 ;
  wire \cycle_count_reg[16]_i_1_n_5 ;
  wire \cycle_count_reg[16]_i_1_n_6 ;
  wire \cycle_count_reg[16]_i_1_n_7 ;
  wire \cycle_count_reg[20]_i_1_n_0 ;
  wire \cycle_count_reg[20]_i_1_n_1 ;
  wire \cycle_count_reg[20]_i_1_n_2 ;
  wire \cycle_count_reg[20]_i_1_n_3 ;
  wire \cycle_count_reg[20]_i_1_n_4 ;
  wire \cycle_count_reg[20]_i_1_n_5 ;
  wire \cycle_count_reg[20]_i_1_n_6 ;
  wire \cycle_count_reg[20]_i_1_n_7 ;
  wire \cycle_count_reg[24]_i_1_n_0 ;
  wire \cycle_count_reg[24]_i_1_n_1 ;
  wire \cycle_count_reg[24]_i_1_n_2 ;
  wire \cycle_count_reg[24]_i_1_n_3 ;
  wire \cycle_count_reg[24]_i_1_n_4 ;
  wire \cycle_count_reg[24]_i_1_n_5 ;
  wire \cycle_count_reg[24]_i_1_n_6 ;
  wire \cycle_count_reg[24]_i_1_n_7 ;
  wire \cycle_count_reg[28]_i_1_n_3 ;
  wire \cycle_count_reg[28]_i_1_n_6 ;
  wire \cycle_count_reg[28]_i_1_n_7 ;
  wire \cycle_count_reg[4]_i_1_n_0 ;
  wire \cycle_count_reg[4]_i_1_n_1 ;
  wire \cycle_count_reg[4]_i_1_n_2 ;
  wire \cycle_count_reg[4]_i_1_n_3 ;
  wire \cycle_count_reg[4]_i_1_n_4 ;
  wire \cycle_count_reg[4]_i_1_n_5 ;
  wire \cycle_count_reg[4]_i_1_n_6 ;
  wire \cycle_count_reg[4]_i_1_n_7 ;
  wire \cycle_count_reg[8]_i_1_n_0 ;
  wire \cycle_count_reg[8]_i_1_n_1 ;
  wire \cycle_count_reg[8]_i_1_n_2 ;
  wire \cycle_count_reg[8]_i_1_n_3 ;
  wire \cycle_count_reg[8]_i_1_n_4 ;
  wire \cycle_count_reg[8]_i_1_n_5 ;
  wire \cycle_count_reg[8]_i_1_n_6 ;
  wire \cycle_count_reg[8]_i_1_n_7 ;
  wire [36:0]d;
  wire [2:1]nextstate;
  wire [5:0]p_0_in;
  wire [25:0]qdpo;
  wire [2:0]state;
  wire wea_ext_ISA;
  wire [24:15]NLW_IR_qdpo_UNCONNECTED;
  wire [3:1]\NLW_cycle_count_reg[28]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_cycle_count_reg[28]_i_1_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'hF100FFFF)) 
    \FSM_sequential_state[0]_i_1 
       (.I0(\FSM_sequential_state_reg[1]_0 ),
        .I1(\FSM_sequential_state[1]_i_3_n_0 ),
        .I2(state[1]),
        .I3(state[2]),
        .I4(state[0]),
        .O(\FSM_sequential_state[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF0EE0000FFFF00)) 
    \FSM_sequential_state[1]_i_1 
       (.I0(\FSM_sequential_state_reg[1]_0 ),
        .I1(\FSM_sequential_state[1]_i_3_n_0 ),
        .I2(\FSM_sequential_state[2]_i_2_n_0 ),
        .I3(state[0]),
        .I4(state[1]),
        .I5(state[2]),
        .O(nextstate[1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000001)) 
    \FSM_sequential_state[1]_i_3 
       (.I0(qdpo[2]),
        .I1(qdpo[3]),
        .I2(qdpo[4]),
        .I3(qdpo[0]),
        .I4(qdpo[1]),
        .I5(command_we1),
        .O(\FSM_sequential_state[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFC8C)) 
    \FSM_sequential_state[2]_i_1 
       (.I0(\FSM_sequential_state[2]_i_2_n_0 ),
        .I1(state[2]),
        .I2(state[1]),
        .I3(state[0]),
        .O(nextstate[2]));
  LUT5 #(
    .INIT(32'h80000000)) 
    \FSM_sequential_state[2]_i_2 
       (.I0(qdpo[4]),
        .I1(qdpo[3]),
        .I2(qdpo[1]),
        .I3(qdpo[0]),
        .I4(qdpo[2]),
        .O(\FSM_sequential_state[2]_i_2_n_0 ));
  (* FSM_ENCODED_STATES = "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111" *) 
  FDRE \FSM_sequential_state_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\FSM_sequential_state[0]_i_1_n_0 ),
        .Q(state[0]),
        .R(control_high_word[0]));
  (* FSM_ENCODED_STATES = "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111" *) 
  FDRE \FSM_sequential_state_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(nextstate[1]),
        .Q(state[1]),
        .R(control_high_word[0]));
  (* FSM_ENCODED_STATES = "iSTATE:000,iSTATE0:010,iSTATE1:011,iSTATE2:100,iSTATE3:101,iSTATE4:110,iSTATE5:001,iSTATE6:111" *) 
  FDRE \FSM_sequential_state_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(nextstate[2]),
        .Q(state[2]),
        .R(control_high_word[0]));
  (* CHECK_LICENSE_TYPE = "INS_RAM,dist_mem_gen_v8_0_13,{}" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  (* x_core_info = "dist_mem_gen_v8_0_13,Vivado 2019.1" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_INS_RAM IR
       (.a(control_low_word[5:0]),
        .clk(1'b0),
        .d(d),
        .dpra(IR_address_reg),
        .qdpo({command_we1,qdpo[25:15],NLW_IR_qdpo_UNCONNECTED[24:15],qdpo[14:0]}),
        .qdpo_clk(clk),
        .we(wea_ext_ISA));
  LUT1 #(
    .INIT(2'h1)) 
    \IR_address[0]_i_1 
       (.I0(IR_address_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \IR_address[1]_i_1 
       (.I0(IR_address_reg[1]),
        .I1(IR_address_reg[0]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \IR_address[2]_i_1 
       (.I0(IR_address_reg[2]),
        .I1(IR_address_reg[0]),
        .I2(IR_address_reg[1]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \IR_address[3]_i_1 
       (.I0(IR_address_reg[3]),
        .I1(IR_address_reg[1]),
        .I2(IR_address_reg[0]),
        .I3(IR_address_reg[2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \IR_address[4]_i_1 
       (.I0(IR_address_reg[4]),
        .I1(IR_address_reg[2]),
        .I2(IR_address_reg[0]),
        .I3(IR_address_reg[1]),
        .I4(IR_address_reg[3]),
        .O(p_0_in[4]));
  LUT2 #(
    .INIT(4'hB)) 
    \IR_address[5]_i_1 
       (.I0(control_high_word[0]),
        .I1(control_high_word[1]),
        .O(IR_address0));
  LUT3 #(
    .INIT(8'h41)) 
    \IR_address[5]_i_2 
       (.I0(state[0]),
        .I1(state[2]),
        .I2(state[1]),
        .O(\IR_address[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \IR_address[5]_i_3 
       (.I0(IR_address_reg[5]),
        .I1(IR_address_reg[3]),
        .I2(IR_address_reg[1]),
        .I3(IR_address_reg[0]),
        .I4(IR_address_reg[2]),
        .I5(IR_address_reg[4]),
        .O(p_0_in[5]));
  FDRE \IR_address_reg[0] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[0]),
        .Q(IR_address_reg[0]),
        .R(IR_address0));
  FDRE \IR_address_reg[1] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[1]),
        .Q(IR_address_reg[1]),
        .R(IR_address0));
  FDRE \IR_address_reg[2] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[2]),
        .Q(IR_address_reg[2]),
        .R(IR_address0));
  FDRE \IR_address_reg[3] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[3]),
        .Q(IR_address_reg[3]),
        .R(IR_address0));
  FDRE \IR_address_reg[4] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[4]),
        .Q(IR_address_reg[4]),
        .R(IR_address0));
  FDRE \IR_address_reg[5] 
       (.C(clk),
        .CE(\IR_address[5]_i_2_n_0 ),
        .D(p_0_in[5]),
        .Q(IR_address_reg[5]),
        .R(IR_address0));
  LUT2 #(
    .INIT(4'h8)) 
    IR_i_1
       (.I0(control_low_word[7]),
        .I1(control_low_word[6]),
        .O(wea_ext_ISA));
  LUT1 #(
    .INIT(2'h1)) 
    \cycle_count[0]_i_2 
       (.I0(D[1]),
        .O(\cycle_count[0]_i_2_n_0 ));
  FDRE \cycle_count_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[0]_i_1_n_7 ),
        .Q(D[1]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\cycle_count_reg[0]_i_1_n_0 ,\cycle_count_reg[0]_i_1_n_1 ,\cycle_count_reg[0]_i_1_n_2 ,\cycle_count_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\cycle_count_reg[0]_i_1_n_4 ,\cycle_count_reg[0]_i_1_n_5 ,\cycle_count_reg[0]_i_1_n_6 ,\cycle_count_reg[0]_i_1_n_7 }),
        .S({D[4:2],\cycle_count[0]_i_2_n_0 }));
  FDRE \cycle_count_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[8]_i_1_n_5 ),
        .Q(D[11]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[8]_i_1_n_4 ),
        .Q(D[12]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[12]_i_1_n_7 ),
        .Q(D[13]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[12]_i_1 
       (.CI(\cycle_count_reg[8]_i_1_n_0 ),
        .CO({\cycle_count_reg[12]_i_1_n_0 ,\cycle_count_reg[12]_i_1_n_1 ,\cycle_count_reg[12]_i_1_n_2 ,\cycle_count_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[12]_i_1_n_4 ,\cycle_count_reg[12]_i_1_n_5 ,\cycle_count_reg[12]_i_1_n_6 ,\cycle_count_reg[12]_i_1_n_7 }),
        .S(D[16:13]));
  FDRE \cycle_count_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[12]_i_1_n_6 ),
        .Q(D[14]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[12]_i_1_n_5 ),
        .Q(D[15]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[12]_i_1_n_4 ),
        .Q(D[16]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[16]_i_1_n_7 ),
        .Q(D[17]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[16]_i_1 
       (.CI(\cycle_count_reg[12]_i_1_n_0 ),
        .CO({\cycle_count_reg[16]_i_1_n_0 ,\cycle_count_reg[16]_i_1_n_1 ,\cycle_count_reg[16]_i_1_n_2 ,\cycle_count_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[16]_i_1_n_4 ,\cycle_count_reg[16]_i_1_n_5 ,\cycle_count_reg[16]_i_1_n_6 ,\cycle_count_reg[16]_i_1_n_7 }),
        .S(D[20:17]));
  FDRE \cycle_count_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[16]_i_1_n_6 ),
        .Q(D[18]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[16]_i_1_n_5 ),
        .Q(D[19]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[16]_i_1_n_4 ),
        .Q(D[20]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[0]_i_1_n_6 ),
        .Q(D[2]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[20]_i_1_n_7 ),
        .Q(D[21]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[20]_i_1 
       (.CI(\cycle_count_reg[16]_i_1_n_0 ),
        .CO({\cycle_count_reg[20]_i_1_n_0 ,\cycle_count_reg[20]_i_1_n_1 ,\cycle_count_reg[20]_i_1_n_2 ,\cycle_count_reg[20]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[20]_i_1_n_4 ,\cycle_count_reg[20]_i_1_n_5 ,\cycle_count_reg[20]_i_1_n_6 ,\cycle_count_reg[20]_i_1_n_7 }),
        .S(D[24:21]));
  FDRE \cycle_count_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[20]_i_1_n_6 ),
        .Q(D[22]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[20]_i_1_n_5 ),
        .Q(D[23]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[20]_i_1_n_4 ),
        .Q(D[24]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[24]_i_1_n_7 ),
        .Q(D[25]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[24]_i_1 
       (.CI(\cycle_count_reg[20]_i_1_n_0 ),
        .CO({\cycle_count_reg[24]_i_1_n_0 ,\cycle_count_reg[24]_i_1_n_1 ,\cycle_count_reg[24]_i_1_n_2 ,\cycle_count_reg[24]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[24]_i_1_n_4 ,\cycle_count_reg[24]_i_1_n_5 ,\cycle_count_reg[24]_i_1_n_6 ,\cycle_count_reg[24]_i_1_n_7 }),
        .S(D[28:25]));
  FDRE \cycle_count_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[24]_i_1_n_6 ),
        .Q(D[26]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[24]_i_1_n_5 ),
        .Q(D[27]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[24]_i_1_n_4 ),
        .Q(D[28]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[28]_i_1_n_7 ),
        .Q(D[29]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[28]_i_1 
       (.CI(\cycle_count_reg[24]_i_1_n_0 ),
        .CO({\NLW_cycle_count_reg[28]_i_1_CO_UNCONNECTED [3:1],\cycle_count_reg[28]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_cycle_count_reg[28]_i_1_O_UNCONNECTED [3:2],\cycle_count_reg[28]_i_1_n_6 ,\cycle_count_reg[28]_i_1_n_7 }),
        .S({1'b0,1'b0,D[30:29]}));
  FDRE \cycle_count_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[28]_i_1_n_6 ),
        .Q(D[30]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[0]_i_1_n_5 ),
        .Q(D[3]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[0]_i_1_n_4 ),
        .Q(D[4]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[4]_i_1_n_7 ),
        .Q(D[5]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[4]_i_1 
       (.CI(\cycle_count_reg[0]_i_1_n_0 ),
        .CO({\cycle_count_reg[4]_i_1_n_0 ,\cycle_count_reg[4]_i_1_n_1 ,\cycle_count_reg[4]_i_1_n_2 ,\cycle_count_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[4]_i_1_n_4 ,\cycle_count_reg[4]_i_1_n_5 ,\cycle_count_reg[4]_i_1_n_6 ,\cycle_count_reg[4]_i_1_n_7 }),
        .S(D[8:5]));
  FDRE \cycle_count_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[4]_i_1_n_6 ),
        .Q(D[6]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[4]_i_1_n_5 ),
        .Q(D[7]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[4]_i_1_n_4 ),
        .Q(D[8]),
        .R(control_high_word[0]));
  FDRE \cycle_count_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[8]_i_1_n_7 ),
        .Q(D[9]),
        .R(control_high_word[0]));
  CARRY4 \cycle_count_reg[8]_i_1 
       (.CI(\cycle_count_reg[4]_i_1_n_0 ),
        .CO({\cycle_count_reg[8]_i_1_n_0 ,\cycle_count_reg[8]_i_1_n_1 ,\cycle_count_reg[8]_i_1_n_2 ,\cycle_count_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\cycle_count_reg[8]_i_1_n_4 ,\cycle_count_reg[8]_i_1_n_5 ,\cycle_count_reg[8]_i_1_n_6 ,\cycle_count_reg[8]_i_1_n_7 }),
        .S(D[12:9]));
  FDRE \cycle_count_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\cycle_count_reg[8]_i_1_n_6 ),
        .Q(D[10]),
        .R(control_high_word[0]));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \status[0]_i_1 
       (.I0(state[2]),
        .I1(state[0]),
        .I2(state[1]),
        .O(D[0]));
endmodule

(* ORIG_REF_NAME = "TRNG_RO" *) (* keep_hierarchy = "true" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO
   (en,
    rng_reg,
    rng_ready);
  input en;
  output [63:0]rng_reg;
  output rng_ready;

  wire \bit_counter[2]_i_1_n_0 ;
  wire [5:0]bit_counter_reg;
  wire clear;
  wire clk;
  wire en;
  wire [5:0]p_0_in;
  wire rng_ready;
  wire [63:0]rng_reg;
  wire ro_bit_out;
  wire ro_sample_clk;
  wire ro_sample_clk_div16;
  wire ro_sample_clk_div16_i_1_n_0;
  wire ro_sample_clk_div2;
  wire ro_sample_clk_div2_i_1_n_0;
  wire ro_sample_clk_div32_i_1_n_0;
  wire ro_sample_clk_div4;
  wire ro_sample_clk_div4_i_1_n_0;
  wire ro_sample_clk_div8;
  wire ro_sample_clk_div8_i_1_n_0;

  LUT1 #(
    .INIT(2'h1)) 
    \bit_counter[0]_i_1 
       (.I0(bit_counter_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \bit_counter[1]_i_1 
       (.I0(bit_counter_reg[0]),
        .I1(bit_counter_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \bit_counter[2]_i_1 
       (.I0(bit_counter_reg[1]),
        .I1(bit_counter_reg[0]),
        .I2(bit_counter_reg[2]),
        .O(\bit_counter[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \bit_counter[3]_i_1 
       (.I0(bit_counter_reg[1]),
        .I1(bit_counter_reg[0]),
        .I2(bit_counter_reg[2]),
        .I3(bit_counter_reg[3]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \bit_counter[4]_i_1 
       (.I0(bit_counter_reg[2]),
        .I1(bit_counter_reg[0]),
        .I2(bit_counter_reg[1]),
        .I3(bit_counter_reg[3]),
        .I4(bit_counter_reg[4]),
        .O(p_0_in[4]));
  LUT1 #(
    .INIT(2'h1)) 
    \bit_counter[5]_i_1 
       (.I0(en),
        .O(clear));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \bit_counter[5]_i_2 
       (.I0(bit_counter_reg[3]),
        .I1(bit_counter_reg[1]),
        .I2(bit_counter_reg[0]),
        .I3(bit_counter_reg[2]),
        .I4(bit_counter_reg[4]),
        .I5(bit_counter_reg[5]),
        .O(p_0_in[5]));
  FDRE \bit_counter_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(bit_counter_reg[0]),
        .R(clear));
  FDRE \bit_counter_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(bit_counter_reg[1]),
        .R(clear));
  FDRE \bit_counter_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\bit_counter[2]_i_1_n_0 ),
        .Q(bit_counter_reg[2]),
        .R(clear));
  FDRE \bit_counter_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(bit_counter_reg[3]),
        .R(clear));
  FDRE \bit_counter_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(bit_counter_reg[4]),
        .R(clear));
  FDRE \bit_counter_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(p_0_in[5]),
        .Q(bit_counter_reg[5]),
        .R(clear));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    rng_ready_INST_0
       (.I0(bit_counter_reg[3]),
        .I1(bit_counter_reg[5]),
        .I2(bit_counter_reg[4]),
        .I3(bit_counter_reg[2]),
        .I4(bit_counter_reg[0]),
        .I5(bit_counter_reg[1]),
        .O(rng_ready));
  FDRE \rng_reg_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(ro_bit_out),
        .Q(rng_reg[0]),
        .R(1'b0));
  FDRE \rng_reg_reg[10] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[9]),
        .Q(rng_reg[10]),
        .R(1'b0));
  FDRE \rng_reg_reg[11] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[10]),
        .Q(rng_reg[11]),
        .R(1'b0));
  FDRE \rng_reg_reg[12] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[11]),
        .Q(rng_reg[12]),
        .R(1'b0));
  FDRE \rng_reg_reg[13] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[12]),
        .Q(rng_reg[13]),
        .R(1'b0));
  FDRE \rng_reg_reg[14] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[13]),
        .Q(rng_reg[14]),
        .R(1'b0));
  FDRE \rng_reg_reg[15] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[14]),
        .Q(rng_reg[15]),
        .R(1'b0));
  FDRE \rng_reg_reg[16] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[15]),
        .Q(rng_reg[16]),
        .R(1'b0));
  FDRE \rng_reg_reg[17] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[16]),
        .Q(rng_reg[17]),
        .R(1'b0));
  FDRE \rng_reg_reg[18] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[17]),
        .Q(rng_reg[18]),
        .R(1'b0));
  FDRE \rng_reg_reg[19] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[18]),
        .Q(rng_reg[19]),
        .R(1'b0));
  FDRE \rng_reg_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[0]),
        .Q(rng_reg[1]),
        .R(1'b0));
  FDRE \rng_reg_reg[20] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[19]),
        .Q(rng_reg[20]),
        .R(1'b0));
  FDRE \rng_reg_reg[21] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[20]),
        .Q(rng_reg[21]),
        .R(1'b0));
  FDRE \rng_reg_reg[22] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[21]),
        .Q(rng_reg[22]),
        .R(1'b0));
  FDRE \rng_reg_reg[23] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[22]),
        .Q(rng_reg[23]),
        .R(1'b0));
  FDRE \rng_reg_reg[24] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[23]),
        .Q(rng_reg[24]),
        .R(1'b0));
  FDRE \rng_reg_reg[25] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[24]),
        .Q(rng_reg[25]),
        .R(1'b0));
  FDRE \rng_reg_reg[26] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[25]),
        .Q(rng_reg[26]),
        .R(1'b0));
  FDRE \rng_reg_reg[27] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[26]),
        .Q(rng_reg[27]),
        .R(1'b0));
  FDRE \rng_reg_reg[28] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[27]),
        .Q(rng_reg[28]),
        .R(1'b0));
  FDRE \rng_reg_reg[29] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[28]),
        .Q(rng_reg[29]),
        .R(1'b0));
  FDRE \rng_reg_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[1]),
        .Q(rng_reg[2]),
        .R(1'b0));
  FDRE \rng_reg_reg[30] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[29]),
        .Q(rng_reg[30]),
        .R(1'b0));
  FDRE \rng_reg_reg[31] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[30]),
        .Q(rng_reg[31]),
        .R(1'b0));
  FDRE \rng_reg_reg[32] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[31]),
        .Q(rng_reg[32]),
        .R(1'b0));
  FDRE \rng_reg_reg[33] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[32]),
        .Q(rng_reg[33]),
        .R(1'b0));
  FDRE \rng_reg_reg[34] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[33]),
        .Q(rng_reg[34]),
        .R(1'b0));
  FDRE \rng_reg_reg[35] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[34]),
        .Q(rng_reg[35]),
        .R(1'b0));
  FDRE \rng_reg_reg[36] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[35]),
        .Q(rng_reg[36]),
        .R(1'b0));
  FDRE \rng_reg_reg[37] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[36]),
        .Q(rng_reg[37]),
        .R(1'b0));
  FDRE \rng_reg_reg[38] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[37]),
        .Q(rng_reg[38]),
        .R(1'b0));
  FDRE \rng_reg_reg[39] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[38]),
        .Q(rng_reg[39]),
        .R(1'b0));
  FDRE \rng_reg_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[2]),
        .Q(rng_reg[3]),
        .R(1'b0));
  FDRE \rng_reg_reg[40] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[39]),
        .Q(rng_reg[40]),
        .R(1'b0));
  FDRE \rng_reg_reg[41] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[40]),
        .Q(rng_reg[41]),
        .R(1'b0));
  FDRE \rng_reg_reg[42] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[41]),
        .Q(rng_reg[42]),
        .R(1'b0));
  FDRE \rng_reg_reg[43] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[42]),
        .Q(rng_reg[43]),
        .R(1'b0));
  FDRE \rng_reg_reg[44] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[43]),
        .Q(rng_reg[44]),
        .R(1'b0));
  FDRE \rng_reg_reg[45] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[44]),
        .Q(rng_reg[45]),
        .R(1'b0));
  FDRE \rng_reg_reg[46] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[45]),
        .Q(rng_reg[46]),
        .R(1'b0));
  FDRE \rng_reg_reg[47] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[46]),
        .Q(rng_reg[47]),
        .R(1'b0));
  FDRE \rng_reg_reg[48] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[47]),
        .Q(rng_reg[48]),
        .R(1'b0));
  FDRE \rng_reg_reg[49] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[48]),
        .Q(rng_reg[49]),
        .R(1'b0));
  FDRE \rng_reg_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[3]),
        .Q(rng_reg[4]),
        .R(1'b0));
  FDRE \rng_reg_reg[50] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[49]),
        .Q(rng_reg[50]),
        .R(1'b0));
  FDRE \rng_reg_reg[51] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[50]),
        .Q(rng_reg[51]),
        .R(1'b0));
  FDRE \rng_reg_reg[52] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[51]),
        .Q(rng_reg[52]),
        .R(1'b0));
  FDRE \rng_reg_reg[53] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[52]),
        .Q(rng_reg[53]),
        .R(1'b0));
  FDRE \rng_reg_reg[54] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[53]),
        .Q(rng_reg[54]),
        .R(1'b0));
  FDRE \rng_reg_reg[55] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[54]),
        .Q(rng_reg[55]),
        .R(1'b0));
  FDRE \rng_reg_reg[56] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[55]),
        .Q(rng_reg[56]),
        .R(1'b0));
  FDRE \rng_reg_reg[57] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[56]),
        .Q(rng_reg[57]),
        .R(1'b0));
  FDRE \rng_reg_reg[58] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[57]),
        .Q(rng_reg[58]),
        .R(1'b0));
  FDRE \rng_reg_reg[59] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[58]),
        .Q(rng_reg[59]),
        .R(1'b0));
  FDRE \rng_reg_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[4]),
        .Q(rng_reg[5]),
        .R(1'b0));
  FDRE \rng_reg_reg[60] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[59]),
        .Q(rng_reg[60]),
        .R(1'b0));
  FDRE \rng_reg_reg[61] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[60]),
        .Q(rng_reg[61]),
        .R(1'b0));
  FDRE \rng_reg_reg[62] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[61]),
        .Q(rng_reg[62]),
        .R(1'b0));
  FDRE \rng_reg_reg[63] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[62]),
        .Q(rng_reg[63]),
        .R(1'b0));
  FDRE \rng_reg_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[5]),
        .Q(rng_reg[6]),
        .R(1'b0));
  FDRE \rng_reg_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[6]),
        .Q(rng_reg[7]),
        .R(1'b0));
  FDRE \rng_reg_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[7]),
        .Q(rng_reg[8]),
        .R(1'b0));
  FDRE \rng_reg_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(rng_reg[8]),
        .Q(rng_reg[9]),
        .R(1'b0));
  (* KEEP_HIERARCHY = "true" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv ro_0
       (.bit_out(ro_bit_out),
        .en(en));
  (* KEEP_HIERARCHY = "true" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv ro_sample
       (.bit_out(ro_sample_clk),
        .en(en));
  LUT1 #(
    .INIT(2'h1)) 
    ro_sample_clk_div16_i_1
       (.I0(ro_sample_clk_div16),
        .O(ro_sample_clk_div16_i_1_n_0));
  FDRE ro_sample_clk_div16_reg
       (.C(ro_sample_clk_div8),
        .CE(1'b1),
        .D(ro_sample_clk_div16_i_1_n_0),
        .Q(ro_sample_clk_div16),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    ro_sample_clk_div2_i_1
       (.I0(ro_sample_clk_div2),
        .O(ro_sample_clk_div2_i_1_n_0));
  FDRE ro_sample_clk_div2_reg
       (.C(ro_sample_clk),
        .CE(1'b1),
        .D(ro_sample_clk_div2_i_1_n_0),
        .Q(ro_sample_clk_div2),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    ro_sample_clk_div32_i_1
       (.I0(clk),
        .O(ro_sample_clk_div32_i_1_n_0));
  FDRE ro_sample_clk_div32_reg
       (.C(ro_sample_clk_div16),
        .CE(1'b1),
        .D(ro_sample_clk_div32_i_1_n_0),
        .Q(clk),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    ro_sample_clk_div4_i_1
       (.I0(ro_sample_clk_div4),
        .O(ro_sample_clk_div4_i_1_n_0));
  FDRE ro_sample_clk_div4_reg
       (.C(ro_sample_clk_div2),
        .CE(1'b1),
        .D(ro_sample_clk_div4_i_1_n_0),
        .Q(ro_sample_clk_div4),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    ro_sample_clk_div8_i_1
       (.I0(ro_sample_clk_div8),
        .O(ro_sample_clk_div8_i_1_n_0));
  FDRE ro_sample_clk_div8_reg
       (.C(ro_sample_clk_div4),
        .CE(1'b1),
        .D(ro_sample_clk_div8_i_1_n_0),
        .Q(ro_sample_clk_div8),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "TRNG_wrapper" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_wrapper
   (\command_reg0_reg[0] ,
    dina,
    wea,
    S,
    \command_reg0_reg[28] ,
    \command_reg0_reg[32] ,
    error_reg_0,
    clk,
    Q,
    d,
    dina_ext_high_word,
    control_low_word,
    error_trng_reg_reg,
    D);
  output \command_reg0_reg[0] ;
  output [63:0]dina;
  output [0:0]wea;
  output [1:0]S;
  output [3:0]\command_reg0_reg[28] ;
  output [3:0]\command_reg0_reg[32] ;
  output error_reg_0;
  input clk;
  input [24:0]Q;
  input [36:0]d;
  input [26:0]dina_ext_high_word;
  input [11:0]control_low_word;
  input error_trng_reg_reg;
  input [0:0]D;

  wire BR_i_66_n_0;
  wire [0:0]D;
  wire [24:0]Q;
  wire [1:0]S;
  wire bitgen_done;
  wire bitgen_done_carry_i_1_n_0;
  wire bitgen_done_carry_i_2_n_0;
  wire bitgen_done_carry_i_3_n_0;
  wire bitgen_done_carry_i_4_n_0;
  wire bitgen_done_carry_n_1;
  wire bitgen_done_carry_n_2;
  wire bitgen_done_carry_n_3;
  wire clk;
  wire \command_reg0_reg[0] ;
  wire [3:0]\command_reg0_reg[28] ;
  wire [3:0]\command_reg0_reg[32] ;
  wire [11:0]control_low_word;
  wire [36:0]d;
  wire [63:0]dina;
  wire [26:0]dina_ext_high_word;
  wire enable_TRO;
  wire enable_TRO_for_bitgen;
  wire enable_TRO_for_bitgen_i_1_n_0;
  wire error_reg_0;
  wire error_trng;
  wire error_trng_reg_reg;
  wire rng_ready;
  wire stat_error;
  wire [63:0]trng_out;
  wire trng_rst;
  wire trng_wea;
  wire [0:0]wea;
  wire write_address1;
  wire write_address1_carry__0_i_1_n_0;
  wire write_address1_carry__0_i_2_n_0;
  wire write_address1_carry_i_1_n_0;
  wire write_address1_carry_i_2_n_0;
  wire write_address1_carry_i_3_n_0;
  wire write_address1_carry_i_4_n_0;
  wire write_address1_carry_i_5_n_0;
  wire write_address1_carry_i_6_n_0;
  wire write_address1_carry_i_7_n_0;
  wire write_address1_carry_i_8_n_0;
  wire write_address1_carry_n_0;
  wire write_address1_carry_n_1;
  wire write_address1_carry_n_2;
  wire write_address1_carry_n_3;
  wire \write_address[0]_i_1_n_0 ;
  wire \write_address[1]_i_1_n_0 ;
  wire \write_address[2]_i_1_n_0 ;
  wire \write_address[3]_i_1_n_0 ;
  wire \write_address[3]_i_2_n_0 ;
  wire \write_address[4]_i_1_n_0 ;
  wire \write_address[5]_i_1_n_0 ;
  wire \write_address[6]_i_1_n_0 ;
  wire \write_address[7]_i_1_n_0 ;
  wire \write_address[7]_i_2_n_0 ;
  wire \write_address[8]_i_1_n_0 ;
  wire \write_address[8]_i_2_n_0 ;
  wire \write_address[9]_i_1_n_0 ;
  wire [9:0]write_address_reg;
  wire write_rng_data0;
  wire [3:0]NLW_bitgen_done_carry_O_UNCONNECTED;
  wire [3:0]NLW_write_address1_carry_O_UNCONNECTED;
  wire [3:1]NLW_write_address1_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_write_address1_carry__0_O_UNCONNECTED;

  LUT4 #(
    .INIT(16'h88B8)) 
    BR_i_1
       (.I0(trng_wea),
        .I1(BR_i_66_n_0),
        .I2(control_low_word[10]),
        .I3(control_low_word[11]),
        .O(wea));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_10
       (.I0(trng_out[55]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[18]),
        .O(dina[55]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_11
       (.I0(trng_out[54]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[17]),
        .O(dina[54]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_12
       (.I0(trng_out[53]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[16]),
        .O(dina[53]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_13
       (.I0(trng_out[52]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[15]),
        .O(dina[52]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_14
       (.I0(trng_out[51]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[14]),
        .O(dina[51]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_15
       (.I0(trng_out[50]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[13]),
        .O(dina[50]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_16
       (.I0(trng_out[49]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[12]),
        .O(dina[49]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_17
       (.I0(trng_out[48]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[11]),
        .O(dina[48]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_18
       (.I0(trng_out[47]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[10]),
        .O(dina[47]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_19
       (.I0(trng_out[46]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[9]),
        .O(dina[46]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_2
       (.I0(trng_out[63]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[26]),
        .O(dina[63]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_20
       (.I0(trng_out[45]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[8]),
        .O(dina[45]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_21
       (.I0(trng_out[44]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[7]),
        .O(dina[44]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_22
       (.I0(trng_out[43]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[6]),
        .O(dina[43]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_23
       (.I0(trng_out[42]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[5]),
        .O(dina[42]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_24
       (.I0(trng_out[41]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[4]),
        .O(dina[41]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_25
       (.I0(trng_out[40]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[3]),
        .O(dina[40]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_26
       (.I0(trng_out[39]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[2]),
        .O(dina[39]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_27
       (.I0(trng_out[38]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[1]),
        .O(dina[38]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_28
       (.I0(trng_out[37]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[0]),
        .O(dina[37]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_29
       (.I0(trng_out[36]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[36]),
        .O(dina[36]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_3
       (.I0(trng_out[62]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[25]),
        .O(dina[62]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_30
       (.I0(trng_out[35]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[35]),
        .O(dina[35]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_31
       (.I0(trng_out[34]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[34]),
        .O(dina[34]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_32
       (.I0(trng_out[33]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[33]),
        .O(dina[33]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_33
       (.I0(trng_out[32]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[32]),
        .O(dina[32]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_34
       (.I0(trng_out[31]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[31]),
        .O(dina[31]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_35
       (.I0(trng_out[30]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[30]),
        .O(dina[30]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_36
       (.I0(trng_out[29]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[29]),
        .O(dina[29]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_37
       (.I0(trng_out[28]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[28]),
        .O(dina[28]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_38
       (.I0(trng_out[27]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[27]),
        .O(dina[27]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_39
       (.I0(trng_out[26]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[26]),
        .O(dina[26]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_4
       (.I0(trng_out[61]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[24]),
        .O(dina[61]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_40
       (.I0(trng_out[25]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[25]),
        .O(dina[25]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_41
       (.I0(trng_out[24]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[24]),
        .O(dina[24]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_42
       (.I0(trng_out[23]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[23]),
        .O(dina[23]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_43
       (.I0(trng_out[22]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[22]),
        .O(dina[22]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_44
       (.I0(trng_out[21]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[21]),
        .O(dina[21]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_45
       (.I0(trng_out[20]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[20]),
        .O(dina[20]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_46
       (.I0(trng_out[19]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[19]),
        .O(dina[19]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_47
       (.I0(trng_out[18]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[18]),
        .O(dina[18]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_48
       (.I0(trng_out[17]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[17]),
        .O(dina[17]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_49
       (.I0(trng_out[16]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[16]),
        .O(dina[16]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_5
       (.I0(trng_out[60]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[23]),
        .O(dina[60]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_50
       (.I0(trng_out[15]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[15]),
        .O(dina[15]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_51
       (.I0(trng_out[14]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[14]),
        .O(dina[14]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_52
       (.I0(trng_out[13]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[13]),
        .O(dina[13]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_53
       (.I0(trng_out[12]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[12]),
        .O(dina[12]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_54
       (.I0(trng_out[11]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[11]),
        .O(dina[11]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_55
       (.I0(trng_out[10]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[10]),
        .O(dina[10]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_56
       (.I0(trng_out[9]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[9]),
        .O(dina[9]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_57
       (.I0(trng_out[8]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[8]),
        .O(dina[8]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_58
       (.I0(trng_out[7]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[7]),
        .O(dina[7]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_59
       (.I0(trng_out[6]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[6]),
        .O(dina[6]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_6
       (.I0(trng_out[59]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[22]),
        .O(dina[59]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_60
       (.I0(trng_out[5]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[5]),
        .O(dina[5]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_61
       (.I0(trng_out[4]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[4]),
        .O(dina[4]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_62
       (.I0(trng_out[3]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[3]),
        .O(dina[3]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_63
       (.I0(trng_out[2]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[2]),
        .O(dina[2]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_64
       (.I0(trng_out[1]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[1]),
        .O(dina[1]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_65
       (.I0(trng_out[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(d[0]),
        .O(dina[0]));
  LUT4 #(
    .INIT(16'h0040)) 
    BR_i_66
       (.I0(Q[3]),
        .I1(Q[4]),
        .I2(Q[1]),
        .I3(Q[2]),
        .O(BR_i_66_n_0));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_7
       (.I0(trng_out[58]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[21]),
        .O(dina[58]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_8
       (.I0(trng_out[57]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[20]),
        .O(dina[57]));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    BR_i_9
       (.I0(trng_out[56]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(dina_ext_high_word[19]),
        .O(dina[56]));
  cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test STest
       (.CO(bitgen_done),
        .D(D),
        .E(write_rng_data0),
        .Q(Q[4:0]),
        .clk(clk),
        .\command_reg0_reg[0] (\command_reg0_reg[0] ),
        .en(enable_TRO),
        .enable_TRO_for_bitgen(enable_TRO_for_bitgen),
        .error_reg(error_reg_0),
        .error_trng(error_trng),
        .error_trng_reg_reg(BR_i_66_n_0),
        .error_trng_reg_reg_0(error_trng_reg_reg),
        .rng_ready(rng_ready),
        .rng_reg(trng_out),
        .stat_error(stat_error));
  (* KEEP_HIERARCHY = "true" *) 
  cryptoprocessor_ComputeCoreWrapper_0_0_TRNG_RO TRO
       (.en(enable_TRO),
        .rng_ready(rng_ready),
        .rng_reg(trng_out));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__0_i_1
       (.I0(Q[22]),
        .I1(control_low_word[7]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[7]),
        .O(\command_reg0_reg[32] [3]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__0_i_2
       (.I0(Q[21]),
        .I1(control_low_word[6]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[6]),
        .O(\command_reg0_reg[32] [2]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__0_i_3
       (.I0(Q[20]),
        .I1(control_low_word[5]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[5]),
        .O(\command_reg0_reg[32] [1]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__0_i_4
       (.I0(Q[19]),
        .I1(control_low_word[4]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[4]),
        .O(\command_reg0_reg[32] [0]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__1_i_1
       (.I0(Q[24]),
        .I1(control_low_word[9]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[9]),
        .O(S[1]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry__1_i_2
       (.I0(Q[23]),
        .I1(control_low_word[8]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[8]),
        .O(S[0]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry_i_1
       (.I0(Q[18]),
        .I1(control_low_word[3]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[3]),
        .O(\command_reg0_reg[28] [3]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry_i_2
       (.I0(Q[17]),
        .I1(control_low_word[2]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[2]),
        .O(\command_reg0_reg[28] [2]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry_i_3
       (.I0(Q[16]),
        .I1(control_low_word[1]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[1]),
        .O(\command_reg0_reg[28] [1]));
  LUT4 #(
    .INIT(16'h56A6)) 
    addra_carry_i_4
       (.I0(Q[15]),
        .I1(control_low_word[0]),
        .I2(BR_i_66_n_0),
        .I3(write_address_reg[0]),
        .O(\command_reg0_reg[28] [0]));
  CARRY4 bitgen_done_carry
       (.CI(1'b0),
        .CO({bitgen_done,bitgen_done_carry_n_1,bitgen_done_carry_n_2,bitgen_done_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_bitgen_done_carry_O_UNCONNECTED[3:0]),
        .S({bitgen_done_carry_i_1_n_0,bitgen_done_carry_i_2_n_0,bitgen_done_carry_i_3_n_0,bitgen_done_carry_i_4_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    bitgen_done_carry_i_1
       (.I0(Q[14]),
        .I1(write_address_reg[9]),
        .O(bitgen_done_carry_i_1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    bitgen_done_carry_i_2
       (.I0(write_address_reg[6]),
        .I1(Q[11]),
        .I2(write_address_reg[7]),
        .I3(Q[12]),
        .I4(Q[13]),
        .I5(write_address_reg[8]),
        .O(bitgen_done_carry_i_2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    bitgen_done_carry_i_3
       (.I0(write_address_reg[4]),
        .I1(Q[9]),
        .I2(write_address_reg[5]),
        .I3(Q[10]),
        .I4(Q[8]),
        .I5(write_address_reg[3]),
        .O(bitgen_done_carry_i_3_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    bitgen_done_carry_i_4
       (.I0(Q[7]),
        .I1(write_address_reg[2]),
        .I2(write_address_reg[0]),
        .I3(Q[5]),
        .I4(write_address_reg[1]),
        .I5(Q[6]),
        .O(bitgen_done_carry_i_4_n_0));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    enable_TRO_for_bitgen_i_1
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(bitgen_done),
        .O(enable_TRO_for_bitgen_i_1_n_0));
  FDRE enable_TRO_for_bitgen_reg
       (.C(clk),
        .CE(1'b1),
        .D(enable_TRO_for_bitgen_i_1_n_0),
        .Q(enable_TRO_for_bitgen),
        .R(1'b0));
  FDRE error_reg
       (.C(clk),
        .CE(1'b1),
        .D(stat_error),
        .Q(error_trng),
        .R(1'b0));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 write_address1_carry
       (.CI(1'b0),
        .CO({write_address1_carry_n_0,write_address1_carry_n_1,write_address1_carry_n_2,write_address1_carry_n_3}),
        .CYINIT(1'b0),
        .DI({write_address1_carry_i_1_n_0,write_address1_carry_i_2_n_0,write_address1_carry_i_3_n_0,write_address1_carry_i_4_n_0}),
        .O(NLW_write_address1_carry_O_UNCONNECTED[3:0]),
        .S({write_address1_carry_i_5_n_0,write_address1_carry_i_6_n_0,write_address1_carry_i_7_n_0,write_address1_carry_i_8_n_0}));
  (* COMPARATOR_THRESHOLD = "11" *) 
  CARRY4 write_address1_carry__0
       (.CI(write_address1_carry_n_0),
        .CO({NLW_write_address1_carry__0_CO_UNCONNECTED[3:1],write_address1}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,write_address1_carry__0_i_1_n_0}),
        .O(NLW_write_address1_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,write_address1_carry__0_i_2_n_0}));
  LUT4 #(
    .INIT(16'h4D44)) 
    write_address1_carry__0_i_1
       (.I0(write_address_reg[9]),
        .I1(Q[14]),
        .I2(write_address_reg[8]),
        .I3(Q[13]),
        .O(write_address1_carry__0_i_1_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    write_address1_carry__0_i_2
       (.I0(Q[14]),
        .I1(write_address_reg[9]),
        .I2(Q[13]),
        .I3(write_address_reg[8]),
        .O(write_address1_carry__0_i_2_n_0));
  LUT4 #(
    .INIT(16'h44D4)) 
    write_address1_carry_i_1
       (.I0(write_address_reg[7]),
        .I1(Q[12]),
        .I2(Q[11]),
        .I3(write_address_reg[6]),
        .O(write_address1_carry_i_1_n_0));
  LUT4 #(
    .INIT(16'h44D4)) 
    write_address1_carry_i_2
       (.I0(write_address_reg[5]),
        .I1(Q[10]),
        .I2(Q[9]),
        .I3(write_address_reg[4]),
        .O(write_address1_carry_i_2_n_0));
  LUT4 #(
    .INIT(16'h44D4)) 
    write_address1_carry_i_3
       (.I0(write_address_reg[3]),
        .I1(Q[8]),
        .I2(Q[7]),
        .I3(write_address_reg[2]),
        .O(write_address1_carry_i_3_n_0));
  LUT4 #(
    .INIT(16'h44D4)) 
    write_address1_carry_i_4
       (.I0(write_address_reg[1]),
        .I1(Q[6]),
        .I2(Q[5]),
        .I3(write_address_reg[0]),
        .O(write_address1_carry_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    write_address1_carry_i_5
       (.I0(Q[12]),
        .I1(write_address_reg[7]),
        .I2(Q[11]),
        .I3(write_address_reg[6]),
        .O(write_address1_carry_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    write_address1_carry_i_6
       (.I0(Q[10]),
        .I1(write_address_reg[5]),
        .I2(Q[9]),
        .I3(write_address_reg[4]),
        .O(write_address1_carry_i_6_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    write_address1_carry_i_7
       (.I0(Q[7]),
        .I1(write_address_reg[2]),
        .I2(Q[8]),
        .I3(write_address_reg[3]),
        .O(write_address1_carry_i_7_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    write_address1_carry_i_8
       (.I0(Q[6]),
        .I1(write_address_reg[1]),
        .I2(Q[5]),
        .I3(write_address_reg[0]),
        .O(write_address1_carry_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \write_address[0]_i_1 
       (.I0(write_address_reg[0]),
        .I1(write_address1),
        .I2(trng_wea),
        .O(\write_address[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \write_address[1]_i_1 
       (.I0(write_address_reg[1]),
        .I1(write_address_reg[0]),
        .I2(trng_wea),
        .I3(write_address1),
        .O(\write_address[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \write_address[2]_i_1 
       (.I0(write_address_reg[2]),
        .I1(write_address_reg[1]),
        .I2(write_address1),
        .I3(trng_wea),
        .I4(write_address_reg[0]),
        .O(\write_address[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0220)) 
    \write_address[3]_i_1 
       (.I0(BR_i_66_n_0),
        .I1(Q[0]),
        .I2(write_address_reg[3]),
        .I3(\write_address[3]_i_2_n_0 ),
        .O(\write_address[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \write_address[3]_i_2 
       (.I0(write_address_reg[1]),
        .I1(write_address1),
        .I2(trng_wea),
        .I3(write_address_reg[0]),
        .I4(write_address_reg[2]),
        .O(\write_address[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \write_address[4]_i_1 
       (.I0(write_address_reg[4]),
        .I1(\write_address[7]_i_2_n_0 ),
        .O(\write_address[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \write_address[5]_i_1 
       (.I0(write_address_reg[5]),
        .I1(write_address_reg[4]),
        .I2(\write_address[7]_i_2_n_0 ),
        .O(\write_address[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \write_address[6]_i_1 
       (.I0(write_address_reg[6]),
        .I1(write_address_reg[5]),
        .I2(\write_address[7]_i_2_n_0 ),
        .I3(write_address_reg[4]),
        .O(\write_address[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \write_address[7]_i_1 
       (.I0(write_address_reg[7]),
        .I1(write_address_reg[6]),
        .I2(write_address_reg[4]),
        .I3(\write_address[7]_i_2_n_0 ),
        .I4(write_address_reg[5]),
        .O(\write_address[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \write_address[7]_i_2 
       (.I0(write_address_reg[2]),
        .I1(write_address_reg[0]),
        .I2(trng_wea),
        .I3(write_address1),
        .I4(write_address_reg[1]),
        .I5(write_address_reg[3]),
        .O(\write_address[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0600)) 
    \write_address[8]_i_1 
       (.I0(\write_address[8]_i_2_n_0 ),
        .I1(write_address_reg[8]),
        .I2(Q[0]),
        .I3(BR_i_66_n_0),
        .O(\write_address[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \write_address[8]_i_2 
       (.I0(write_address_reg[6]),
        .I1(write_address_reg[4]),
        .I2(\write_address[7]_i_2_n_0 ),
        .I3(write_address_reg[5]),
        .I4(write_address_reg[7]),
        .O(\write_address[8]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \write_address[9]_i_1 
       (.I0(write_address_reg[9]),
        .I1(\write_address[8]_i_2_n_0 ),
        .I2(write_address_reg[8]),
        .O(\write_address[9]_i_1_n_0 ));
  FDRE \write_address_reg[0] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[0]_i_1_n_0 ),
        .Q(write_address_reg[0]),
        .R(trng_rst));
  FDRE \write_address_reg[1] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[1]_i_1_n_0 ),
        .Q(write_address_reg[1]),
        .R(trng_rst));
  FDRE \write_address_reg[2] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[2]_i_1_n_0 ),
        .Q(write_address_reg[2]),
        .R(trng_rst));
  FDRE \write_address_reg[3] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[3]_i_1_n_0 ),
        .Q(write_address_reg[3]),
        .R(1'b0));
  FDRE \write_address_reg[4] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[4]_i_1_n_0 ),
        .Q(write_address_reg[4]),
        .R(trng_rst));
  FDRE \write_address_reg[5] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[5]_i_1_n_0 ),
        .Q(write_address_reg[5]),
        .R(trng_rst));
  FDRE \write_address_reg[6] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[6]_i_1_n_0 ),
        .Q(write_address_reg[6]),
        .R(trng_rst));
  FDRE \write_address_reg[7] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[7]_i_1_n_0 ),
        .Q(write_address_reg[7]),
        .R(trng_rst));
  FDRE \write_address_reg[8] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[8]_i_1_n_0 ),
        .Q(write_address_reg[8]),
        .R(1'b0));
  FDRE \write_address_reg[9] 
       (.C(clk),
        .CE(1'b1),
        .D(\write_address[9]_i_1_n_0 ),
        .Q(write_address_reg[9]),
        .R(trng_rst));
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    write_rng_data_i_1
       (.I0(Q[0]),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(trng_rst));
  FDRE write_rng_data_reg
       (.C(clk),
        .CE(1'b1),
        .D(write_rng_data0),
        .Q(trng_wea),
        .R(trng_rst));
endmodule

(* ORIG_REF_NAME = "ro_3inv" *) (* keep_hierarchy = "true" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_ro_3inv
   (en,
    bit_out);
  input en;
  output bit_out;

  wire en;
  (* DONT_TOUCH *) wire [2:0]inv_chain;

  assign bit_out = inv_chain[2];
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_1
       (.I0(inv_chain[1]),
        .O(inv_chain[2]));
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_2
       (.I0(inv_chain[0]),
        .O(inv_chain[1]));
  LUT2 #(
    .INIT(4'h2)) 
    inv_chain_inferred_i_3
       (.I0(en),
        .I1(inv_chain[2]),
        .O(inv_chain[0]));
endmodule

(* ORIG_REF_NAME = "ro_5inv" *) (* keep_hierarchy = "true" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_ro_5inv
   (en,
    bit_out);
  input en;
  output bit_out;

  wire en;
  (* DONT_TOUCH *) wire [4:0]inv_chain;

  assign bit_out = inv_chain[4];
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_1
       (.I0(inv_chain[3]),
        .O(inv_chain[4]));
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_2
       (.I0(inv_chain[2]),
        .O(inv_chain[3]));
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_3
       (.I0(inv_chain[1]),
        .O(inv_chain[2]));
  LUT1 #(
    .INIT(2'h1)) 
    inv_chain_inferred_i_4
       (.I0(inv_chain[0]),
        .O(inv_chain[1]));
  LUT2 #(
    .INIT(4'h2)) 
    inv_chain_inferred_i_5
       (.I0(en),
        .I1(inv_chain[4]),
        .O(inv_chain[0]));
endmodule

(* ORIG_REF_NAME = "statistical_test" *) 
module cryptoprocessor_ComputeCoreWrapper_0_0_statistical_test
   (stat_error,
    \command_reg0_reg[0] ,
    E,
    en,
    error_reg,
    rng_ready,
    clk,
    CO,
    Q,
    error_trng_reg_reg,
    enable_TRO_for_bitgen,
    rng_reg,
    error_trng,
    error_trng_reg_reg_0,
    D);
  output stat_error;
  output \command_reg0_reg[0] ;
  output [0:0]E;
  output en;
  output error_reg;
  input rng_ready;
  input clk;
  input [0:0]CO;
  input [4:0]Q;
  input error_trng_reg_reg;
  input enable_TRO_for_bitgen;
  input [63:0]rng_reg;
  input error_trng;
  input error_trng_reg_reg_0;
  input [0:0]D;

  wire [0:0]CO;
  wire [0:0]D;
  wire [0:0]E;
  wire [4:0]Q;
  wire clk;
  wire \command_reg0_reg[0] ;
  wire en;
  wire enable_TRO_for_bitgen;
  wire enable_TRO_for_statbits;
  wire enable_TRO_i_1_n_0;
  wire error_reg;
  wire error_trng;
  wire error_trng_reg_reg;
  wire error_trng_reg_reg_0;
  wire i__carry__0_i_10_n_0;
  wire i__carry__0_i_11_n_0;
  wire i__carry__0_i_12_n_0;
  wire i__carry__0_i_13_n_0;
  wire i__carry__0_i_14_n_0;
  wire i__carry__0_i_15_n_0;
  wire i__carry__0_i_16_n_0;
  wire i__carry__0_i_17_n_0;
  wire i__carry__0_i_18_n_0;
  wire i__carry__0_i_19_n_0;
  wire i__carry__0_i_1_n_0;
  wire i__carry__0_i_20_n_0;
  wire i__carry__0_i_21_n_0;
  wire i__carry__0_i_22_n_0;
  wire i__carry__0_i_23_n_0;
  wire i__carry__0_i_24_n_0;
  wire i__carry__0_i_25_n_0;
  wire i__carry__0_i_26_n_0;
  wire i__carry__0_i_27_n_0;
  wire i__carry__0_i_28_n_0;
  wire i__carry__0_i_29_n_0;
  wire i__carry__0_i_2_n_0;
  wire i__carry__0_i_3_n_0;
  wire i__carry__0_i_4_n_0;
  wire i__carry__0_i_5_n_0;
  wire i__carry__0_i_6_n_0;
  wire i__carry__0_i_7_n_0;
  wire i__carry__0_i_8_n_0;
  wire i__carry__0_i_9_n_0;
  wire i__carry_i_10_n_0;
  wire i__carry_i_11_n_0;
  wire i__carry_i_12_n_0;
  wire i__carry_i_13_n_0;
  wire i__carry_i_14_n_0;
  wire i__carry_i_15_n_0;
  wire i__carry_i_16_n_0;
  wire i__carry_i_17_n_0;
  wire i__carry_i_18_n_0;
  wire i__carry_i_19_n_0;
  wire i__carry_i_1_n_0;
  wire i__carry_i_20_n_0;
  wire i__carry_i_21_n_0;
  wire i__carry_i_22_n_0;
  wire i__carry_i_23_n_0;
  wire i__carry_i_24_n_0;
  wire i__carry_i_25_n_0;
  wire i__carry_i_26_n_0;
  wire i__carry_i_27_n_0;
  wire i__carry_i_28_n_0;
  wire i__carry_i_29_n_0;
  wire i__carry_i_2_n_0;
  wire i__carry_i_30_n_0;
  wire i__carry_i_31_n_0;
  wire i__carry_i_32_n_0;
  wire i__carry_i_33_n_0;
  wire i__carry_i_34_n_0;
  wire i__carry_i_35_n_0;
  wire i__carry_i_36_n_0;
  wire i__carry_i_37_n_0;
  wire i__carry_i_38_n_0;
  wire i__carry_i_39_n_0;
  wire i__carry_i_3_n_0;
  wire i__carry_i_40_n_0;
  wire i__carry_i_41_n_0;
  wire i__carry_i_42_n_0;
  wire i__carry_i_43_n_0;
  wire i__carry_i_44_n_0;
  wire i__carry_i_45_n_0;
  wire i__carry_i_46_n_0;
  wire i__carry_i_47_n_0;
  wire i__carry_i_48_n_0;
  wire i__carry_i_49_n_0;
  wire i__carry_i_4_n_0;
  wire i__carry_i_50_n_0;
  wire i__carry_i_51_n_0;
  wire i__carry_i_52_n_0;
  wire i__carry_i_53_n_0;
  wire i__carry_i_54_n_0;
  wire i__carry_i_55_n_0;
  wire i__carry_i_56_n_0;
  wire i__carry_i_57_n_0;
  wire i__carry_i_58_n_0;
  wire i__carry_i_59_n_0;
  wire i__carry_i_5_n_0;
  wire i__carry_i_60_n_0;
  wire i__carry_i_61_n_0;
  wire i__carry_i_62_n_0;
  wire i__carry_i_63_n_0;
  wire i__carry_i_64_n_0;
  wire i__carry_i_65_n_0;
  wire i__carry_i_66_n_0;
  wire i__carry_i_67_n_0;
  wire i__carry_i_68_n_0;
  wire i__carry_i_69_n_0;
  wire i__carry_i_6_n_0;
  wire i__carry_i_70_n_0;
  wire i__carry_i_71_n_0;
  wire i__carry_i_72_n_0;
  wire i__carry_i_73_n_0;
  wire i__carry_i_74_n_0;
  wire i__carry_i_75_n_0;
  wire i__carry_i_7_n_0;
  wire i__carry_i_8_n_0;
  wire i__carry_i_9_n_0;
  wire \num_of_1s0_inferred__0/i__carry__0_n_0 ;
  wire \num_of_1s0_inferred__0/i__carry__0_n_1 ;
  wire \num_of_1s0_inferred__0/i__carry__0_n_2 ;
  wire \num_of_1s0_inferred__0/i__carry__0_n_3 ;
  wire \num_of_1s0_inferred__0/i__carry__1_n_0 ;
  wire \num_of_1s0_inferred__0/i__carry__1_n_1 ;
  wire \num_of_1s0_inferred__0/i__carry__1_n_2 ;
  wire \num_of_1s0_inferred__0/i__carry__1_n_3 ;
  wire \num_of_1s0_inferred__0/i__carry__2_n_0 ;
  wire \num_of_1s0_inferred__0/i__carry__2_n_1 ;
  wire \num_of_1s0_inferred__0/i__carry__2_n_2 ;
  wire \num_of_1s0_inferred__0/i__carry__2_n_3 ;
  wire \num_of_1s0_inferred__0/i__carry__3_n_1 ;
  wire \num_of_1s0_inferred__0/i__carry__3_n_2 ;
  wire \num_of_1s0_inferred__0/i__carry__3_n_3 ;
  wire \num_of_1s0_inferred__0/i__carry_n_0 ;
  wire \num_of_1s0_inferred__0/i__carry_n_1 ;
  wire \num_of_1s0_inferred__0/i__carry_n_2 ;
  wire \num_of_1s0_inferred__0/i__carry_n_3 ;
  wire \num_of_1s_reg_n_0_[0] ;
  wire \num_of_1s_reg_n_0_[10] ;
  wire \num_of_1s_reg_n_0_[11] ;
  wire \num_of_1s_reg_n_0_[12] ;
  wire \num_of_1s_reg_n_0_[13] ;
  wire \num_of_1s_reg_n_0_[14] ;
  wire \num_of_1s_reg_n_0_[15] ;
  wire \num_of_1s_reg_n_0_[16] ;
  wire \num_of_1s_reg_n_0_[17] ;
  wire \num_of_1s_reg_n_0_[18] ;
  wire \num_of_1s_reg_n_0_[19] ;
  wire \num_of_1s_reg_n_0_[1] ;
  wire \num_of_1s_reg_n_0_[2] ;
  wire \num_of_1s_reg_n_0_[3] ;
  wire \num_of_1s_reg_n_0_[4] ;
  wire \num_of_1s_reg_n_0_[5] ;
  wire \num_of_1s_reg_n_0_[6] ;
  wire \num_of_1s_reg_n_0_[7] ;
  wire \num_of_1s_reg_n_0_[8] ;
  wire \num_of_1s_reg_n_0_[9] ;
  wire [19:0]p_0_in;
  wire rng_ready;
  wire rng_ready_d0;
  wire rng_ready_d1;
  wire [63:0]rng_reg;
  wire rng_word_counter0;
  wire \rng_word_counter[0]_i_4_n_0 ;
  wire \rng_word_counter[0]_i_5_n_0 ;
  wire \rng_word_counter[0]_i_6_n_0 ;
  wire \rng_word_counter[0]_i_7_n_0 ;
  wire \rng_word_counter[0]_i_8_n_0 ;
  wire [19:0]rng_word_counter_reg;
  wire \rng_word_counter_reg[0]_i_2_n_0 ;
  wire \rng_word_counter_reg[0]_i_2_n_1 ;
  wire \rng_word_counter_reg[0]_i_2_n_2 ;
  wire \rng_word_counter_reg[0]_i_2_n_3 ;
  wire \rng_word_counter_reg[0]_i_2_n_4 ;
  wire \rng_word_counter_reg[0]_i_2_n_5 ;
  wire \rng_word_counter_reg[0]_i_2_n_6 ;
  wire \rng_word_counter_reg[0]_i_2_n_7 ;
  wire \rng_word_counter_reg[12]_i_1_n_0 ;
  wire \rng_word_counter_reg[12]_i_1_n_1 ;
  wire \rng_word_counter_reg[12]_i_1_n_2 ;
  wire \rng_word_counter_reg[12]_i_1_n_3 ;
  wire \rng_word_counter_reg[12]_i_1_n_4 ;
  wire \rng_word_counter_reg[12]_i_1_n_5 ;
  wire \rng_word_counter_reg[12]_i_1_n_6 ;
  wire \rng_word_counter_reg[12]_i_1_n_7 ;
  wire \rng_word_counter_reg[16]_i_1_n_1 ;
  wire \rng_word_counter_reg[16]_i_1_n_2 ;
  wire \rng_word_counter_reg[16]_i_1_n_3 ;
  wire \rng_word_counter_reg[16]_i_1_n_4 ;
  wire \rng_word_counter_reg[16]_i_1_n_5 ;
  wire \rng_word_counter_reg[16]_i_1_n_6 ;
  wire \rng_word_counter_reg[16]_i_1_n_7 ;
  wire \rng_word_counter_reg[4]_i_1_n_0 ;
  wire \rng_word_counter_reg[4]_i_1_n_1 ;
  wire \rng_word_counter_reg[4]_i_1_n_2 ;
  wire \rng_word_counter_reg[4]_i_1_n_3 ;
  wire \rng_word_counter_reg[4]_i_1_n_4 ;
  wire \rng_word_counter_reg[4]_i_1_n_5 ;
  wire \rng_word_counter_reg[4]_i_1_n_6 ;
  wire \rng_word_counter_reg[4]_i_1_n_7 ;
  wire \rng_word_counter_reg[8]_i_1_n_0 ;
  wire \rng_word_counter_reg[8]_i_1_n_1 ;
  wire \rng_word_counter_reg[8]_i_1_n_2 ;
  wire \rng_word_counter_reg[8]_i_1_n_3 ;
  wire \rng_word_counter_reg[8]_i_1_n_4 ;
  wire \rng_word_counter_reg[8]_i_1_n_5 ;
  wire \rng_word_counter_reg[8]_i_1_n_6 ;
  wire \rng_word_counter_reg[8]_i_1_n_7 ;
  wire stat_done;
  wire stat_error;
  wire stat_error_i_1_n_0;
  wire stat_error_i_2_n_0;
  wire stat_error_i_3_n_0;
  wire stat_error_i_4_n_0;
  wire stat_error_i_5_n_0;
  wire stat_error_i_6_n_0;
  wire stat_error_i_7_n_0;
  wire stat_error_i_8_n_0;
  wire stat_trng_rst;
  wire [3:3]\NLW_num_of_1s0_inferred__0/i__carry__3_CO_UNCONNECTED ;
  wire [3:3]\NLW_rng_word_counter_reg[16]_i_1_CO_UNCONNECTED ;

  LUT4 #(
    .INIT(16'hEA2A)) 
    \FSM_sequential_state[1]_i_2 
       (.I0(CO),
        .I1(Q[0]),
        .I2(error_trng_reg_reg),
        .I3(stat_done),
        .O(\command_reg0_reg[0] ));
  LUT4 #(
    .INIT(16'hEA2A)) 
    TRO_i_1
       (.I0(enable_TRO_for_bitgen),
        .I1(Q[0]),
        .I2(error_trng_reg_reg),
        .I3(enable_TRO_for_statbits),
        .O(en));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    enable_TRO_i_1
       (.I0(stat_done),
        .I1(Q[3]),
        .I2(Q[4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(Q[0]),
        .O(enable_TRO_i_1_n_0));
  FDRE enable_TRO_reg
       (.C(clk),
        .CE(1'b1),
        .D(enable_TRO_i_1_n_0),
        .Q(enable_TRO_for_statbits),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h8B88)) 
    error_trng_reg_i_1
       (.I0(error_trng),
        .I1(\command_reg0_reg[0] ),
        .I2(error_trng_reg_reg_0),
        .I3(D),
        .O(error_reg));
  LUT4 #(
    .INIT(16'hAAA6)) 
    i__carry__0_i_1
       (.I0(\num_of_1s_reg_n_0_[6] ),
        .I1(i__carry__0_i_4_n_0),
        .I2(i__carry__0_i_5_n_0),
        .I3(i__carry__0_i_6_n_0),
        .O(i__carry__0_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'h17)) 
    i__carry__0_i_10
       (.I0(i__carry_i_58_n_0),
        .I1(i__carry_i_59_n_0),
        .I2(i__carry_i_60_n_0),
        .O(i__carry__0_i_10_n_0));
  LUT3 #(
    .INIT(8'h96)) 
    i__carry__0_i_11
       (.I0(i__carry__0_i_16_n_0),
        .I1(i__carry__0_i_17_n_0),
        .I2(i__carry__0_i_18_n_0),
        .O(i__carry__0_i_11_n_0));
  LUT6 #(
    .INIT(64'h8E8E8E718E717171)) 
    i__carry__0_i_12
       (.I0(i__carry__0_i_18_n_0),
        .I1(i__carry__0_i_17_n_0),
        .I2(i__carry__0_i_16_n_0),
        .I3(i__carry__0_i_21_n_0),
        .I4(i__carry__0_i_20_n_0),
        .I5(i__carry__0_i_19_n_0),
        .O(i__carry__0_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'h96FF0096)) 
    i__carry__0_i_13
       (.I0(i__carry__0_i_20_n_0),
        .I1(i__carry__0_i_21_n_0),
        .I2(i__carry__0_i_19_n_0),
        .I3(i__carry_i_46_n_0),
        .I4(i__carry_i_45_n_0),
        .O(i__carry__0_i_13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry__0_i_14
       (.I0(i__carry_i_20_n_0),
        .I1(i__carry_i_21_n_0),
        .I2(i__carry_i_22_n_0),
        .O(i__carry__0_i_14_n_0));
  LUT3 #(
    .INIT(8'h8E)) 
    i__carry__0_i_15
       (.I0(i__carry_i_26_n_0),
        .I1(i__carry_i_25_n_0),
        .I2(i__carry_i_24_n_0),
        .O(i__carry__0_i_15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'hE800FFE8)) 
    i__carry__0_i_16
       (.I0(rng_reg[8]),
        .I1(rng_reg[7]),
        .I2(rng_reg[9]),
        .I3(i__carry__0_i_22_n_0),
        .I4(i__carry__0_i_23_n_0),
        .O(i__carry__0_i_16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'h11171777)) 
    i__carry__0_i_17
       (.I0(i__carry__0_i_24_n_0),
        .I1(i__carry__0_i_25_n_0),
        .I2(rng_reg[18]),
        .I3(rng_reg[17]),
        .I4(rng_reg[16]),
        .O(i__carry__0_i_17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h888E8EEE)) 
    i__carry__0_i_18
       (.I0(i__carry__0_i_26_n_0),
        .I1(i__carry__0_i_27_n_0),
        .I2(rng_reg[27]),
        .I3(rng_reg[26]),
        .I4(rng_reg[25]),
        .O(i__carry__0_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT5 #(
    .INIT(32'h888A8AAA)) 
    i__carry__0_i_19
       (.I0(i__carry__0_i_28_n_0),
        .I1(i__carry__0_i_29_n_0),
        .I2(rng_reg[36]),
        .I3(rng_reg[35]),
        .I4(rng_reg[34]),
        .O(i__carry__0_i_19_n_0));
  LUT6 #(
    .INIT(64'h655965596559AAA9)) 
    i__carry__0_i_2
       (.I0(\num_of_1s_reg_n_0_[5] ),
        .I1(i__carry__0_i_4_n_0),
        .I2(i__carry__0_i_5_n_0),
        .I3(i__carry__0_i_6_n_0),
        .I4(i__carry__0_i_7_n_0),
        .I5(i__carry__0_i_8_n_0),
        .O(i__carry__0_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'h11171777)) 
    i__carry__0_i_20
       (.I0(i__carry_i_64_n_0),
        .I1(i__carry_i_63_n_0),
        .I2(rng_reg[52]),
        .I3(rng_reg[53]),
        .I4(rng_reg[54]),
        .O(i__carry__0_i_20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'h222B2BBB)) 
    i__carry__0_i_21
       (.I0(i__carry_i_62_n_0),
        .I1(i__carry_i_61_n_0),
        .I2(rng_reg[45]),
        .I3(rng_reg[43]),
        .I4(rng_reg[44]),
        .O(i__carry__0_i_21_n_0));
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry__0_i_22
       (.I0(rng_reg[4]),
        .I1(rng_reg[6]),
        .I2(rng_reg[5]),
        .O(i__carry__0_i_22_n_0));
  LUT3 #(
    .INIT(8'h17)) 
    i__carry__0_i_23
       (.I0(rng_reg[2]),
        .I1(rng_reg[1]),
        .I2(rng_reg[3]),
        .O(i__carry__0_i_23_n_0));
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry__0_i_24
       (.I0(rng_reg[10]),
        .I1(rng_reg[12]),
        .I2(rng_reg[11]),
        .O(i__carry__0_i_24_n_0));
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry__0_i_25
       (.I0(rng_reg[15]),
        .I1(rng_reg[14]),
        .I2(rng_reg[13]),
        .O(i__carry__0_i_25_n_0));
  LUT3 #(
    .INIT(8'h17)) 
    i__carry__0_i_26
       (.I0(rng_reg[24]),
        .I1(rng_reg[23]),
        .I2(rng_reg[22]),
        .O(i__carry__0_i_26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'h17)) 
    i__carry__0_i_27
       (.I0(rng_reg[20]),
        .I1(rng_reg[19]),
        .I2(rng_reg[21]),
        .O(i__carry__0_i_27_n_0));
  LUT6 #(
    .INIT(64'h171717FF17FFFFFF)) 
    i__carry__0_i_28
       (.I0(rng_reg[30]),
        .I1(rng_reg[28]),
        .I2(rng_reg[29]),
        .I3(rng_reg[31]),
        .I4(rng_reg[32]),
        .I5(rng_reg[33]),
        .O(i__carry__0_i_28_n_0));
  LUT6 #(
    .INIT(64'h0000001700171717)) 
    i__carry__0_i_29
       (.I0(rng_reg[30]),
        .I1(rng_reg[28]),
        .I2(rng_reg[29]),
        .I3(rng_reg[31]),
        .I4(rng_reg[32]),
        .I5(rng_reg[33]),
        .O(i__carry__0_i_29_n_0));
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry__0_i_3
       (.I0(\num_of_1s_reg_n_0_[4] ),
        .I1(i__carry__0_i_6_n_0),
        .I2(i__carry__0_i_8_n_0),
        .I3(i__carry__0_i_7_n_0),
        .I4(i__carry__0_i_5_n_0),
        .O(i__carry__0_i_3_n_0));
  LUT6 #(
    .INIT(64'h00000000D4FF0000)) 
    i__carry__0_i_4
       (.I0(i__carry__0_i_9_n_0),
        .I1(i__carry__0_i_10_n_0),
        .I2(i__carry__0_i_11_n_0),
        .I3(i__carry__0_i_12_n_0),
        .I4(i__carry__0_i_7_n_0),
        .I5(i__carry__0_i_13_n_0),
        .O(i__carry__0_i_4_n_0));
  LUT5 #(
    .INIT(32'hAE8AEFAE)) 
    i__carry__0_i_5
       (.I0(i__carry_i_8_n_0),
        .I1(i__carry_i_5_n_0),
        .I2(i__carry__0_i_14_n_0),
        .I3(i__carry_i_19_n_0),
        .I4(i__carry_i_6_n_0),
        .O(i__carry__0_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'hFFD4D400)) 
    i__carry__0_i_6
       (.I0(i__carry_i_20_n_0),
        .I1(i__carry_i_22_n_0),
        .I2(i__carry_i_21_n_0),
        .I3(i__carry__0_i_15_n_0),
        .I4(i__carry_i_23_n_0),
        .O(i__carry__0_i_6_n_0));
  LUT6 #(
    .INIT(64'h0000002B002B2B2B)) 
    i__carry__0_i_7
       (.I0(i__carry__0_i_16_n_0),
        .I1(i__carry__0_i_17_n_0),
        .I2(i__carry__0_i_18_n_0),
        .I3(i__carry__0_i_19_n_0),
        .I4(i__carry__0_i_20_n_0),
        .I5(i__carry__0_i_21_n_0),
        .O(i__carry__0_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h00D4D4FF)) 
    i__carry__0_i_8
       (.I0(i__carry__0_i_9_n_0),
        .I1(i__carry__0_i_10_n_0),
        .I2(i__carry__0_i_11_n_0),
        .I3(i__carry__0_i_13_n_0),
        .I4(i__carry__0_i_12_n_0),
        .O(i__carry__0_i_8_n_0));
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry__0_i_9
       (.I0(i__carry_i_27_n_0),
        .I1(i__carry_i_28_n_0),
        .I2(i__carry_i_29_n_0),
        .O(i__carry__0_i_9_n_0));
  LUT6 #(
    .INIT(64'hD42B2BD42BD4D42B)) 
    i__carry_i_1
       (.I0(i__carry_i_5_n_0),
        .I1(i__carry_i_6_n_0),
        .I2(i__carry_i_7_n_0),
        .I3(\num_of_1s_reg_n_0_[3] ),
        .I4(i__carry_i_8_n_0),
        .I5(i__carry_i_9_n_0),
        .O(i__carry_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_10
       (.I0(i__carry_i_27_n_0),
        .I1(i__carry_i_28_n_0),
        .I2(i__carry_i_29_n_0),
        .I3(i__carry_i_30_n_0),
        .I4(i__carry_i_31_n_0),
        .O(i__carry_i_10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_11
       (.I0(i__carry_i_32_n_0),
        .I1(i__carry_i_33_n_0),
        .I2(i__carry_i_34_n_0),
        .I3(i__carry_i_35_n_0),
        .I4(i__carry_i_36_n_0),
        .O(i__carry_i_11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'h2BB2B22B)) 
    i__carry_i_12
       (.I0(i__carry_i_37_n_0),
        .I1(i__carry_i_38_n_0),
        .I2(rng_reg[2]),
        .I3(rng_reg[1]),
        .I4(rng_reg[3]),
        .O(i__carry_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'h2B)) 
    i__carry_i_13
       (.I0(i__carry_i_16_n_0),
        .I1(i__carry_i_15_n_0),
        .I2(i__carry_i_17_n_0),
        .O(i__carry_i_13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT4 #(
    .INIT(16'h0069)) 
    i__carry_i_14
       (.I0(i__carry_i_17_n_0),
        .I1(i__carry_i_16_n_0),
        .I2(i__carry_i_15_n_0),
        .I3(i__carry_i_18_n_0),
        .O(i__carry_i_14_n_0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    i__carry_i_15
       (.I0(i__carry_i_39_n_0),
        .I1(rng_reg[28]),
        .I2(rng_reg[29]),
        .I3(rng_reg[30]),
        .I4(i__carry_i_40_n_0),
        .I5(i__carry_i_41_n_0),
        .O(i__carry_i_15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'h69969669)) 
    i__carry_i_16
       (.I0(rng_reg[50]),
        .I1(rng_reg[51]),
        .I2(rng_reg[49]),
        .I3(i__carry_i_42_n_0),
        .I4(i__carry_i_43_n_0),
        .O(i__carry_i_16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_17
       (.I0(rng_reg[59]),
        .I1(rng_reg[58]),
        .I2(rng_reg[60]),
        .I3(i__carry_i_44_n_0),
        .I4(rng_reg[0]),
        .O(i__carry_i_17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_18
       (.I0(i__carry_i_37_n_0),
        .I1(rng_reg[3]),
        .I2(rng_reg[1]),
        .I3(rng_reg[2]),
        .I4(i__carry_i_38_n_0),
        .O(i__carry_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'hFF969600)) 
    i__carry_i_19
       (.I0(i__carry_i_27_n_0),
        .I1(i__carry_i_28_n_0),
        .I2(i__carry_i_29_n_0),
        .I3(i__carry_i_30_n_0),
        .I4(i__carry_i_31_n_0),
        .O(i__carry_i_19_n_0));
  LUT4 #(
    .INIT(16'h9669)) 
    i__carry_i_2
       (.I0(\num_of_1s_reg_n_0_[2] ),
        .I1(i__carry_i_6_n_0),
        .I2(i__carry_i_7_n_0),
        .I3(i__carry_i_5_n_0),
        .O(i__carry_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_20
       (.I0(i__carry_i_45_n_0),
        .I1(i__carry_i_46_n_0),
        .I2(i__carry_i_47_n_0),
        .I3(i__carry_i_25_n_0),
        .I4(i__carry_i_26_n_0),
        .O(i__carry_i_20_n_0));
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_21
       (.I0(i__carry__0_i_11_n_0),
        .I1(i__carry__0_i_10_n_0),
        .I2(i__carry__0_i_9_n_0),
        .O(i__carry_i_21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h009696FF)) 
    i__carry_i_22
       (.I0(i__carry_i_32_n_0),
        .I1(i__carry_i_33_n_0),
        .I2(i__carry_i_34_n_0),
        .I3(i__carry_i_35_n_0),
        .I4(i__carry_i_36_n_0),
        .O(i__carry_i_22_n_0));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'h2BD4D42B)) 
    i__carry_i_23
       (.I0(i__carry__0_i_9_n_0),
        .I1(i__carry__0_i_10_n_0),
        .I2(i__carry__0_i_11_n_0),
        .I3(i__carry__0_i_12_n_0),
        .I4(i__carry__0_i_13_n_0),
        .O(i__carry_i_23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_24
       (.I0(i__carry_i_47_n_0),
        .I1(i__carry_i_46_n_0),
        .I2(i__carry_i_45_n_0),
        .O(i__carry_i_24_n_0));
  LUT3 #(
    .INIT(8'h2B)) 
    i__carry_i_25
       (.I0(i__carry_i_32_n_0),
        .I1(i__carry_i_33_n_0),
        .I2(i__carry_i_34_n_0),
        .O(i__carry_i_25_n_0));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h17)) 
    i__carry_i_26
       (.I0(i__carry_i_48_n_0),
        .I1(i__carry_i_49_n_0),
        .I2(i__carry_i_50_n_0),
        .O(i__carry_i_26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'hFF696900)) 
    i__carry_i_27
       (.I0(rng_reg[45]),
        .I1(rng_reg[43]),
        .I2(rng_reg[44]),
        .I3(i__carry_i_51_n_0),
        .I4(i__carry_i_52_n_0),
        .O(i__carry_i_27_n_0));
  LUT5 #(
    .INIT(32'h2882AAAA)) 
    i__carry_i_28
       (.I0(i__carry_i_53_n_0),
        .I1(rng_reg[30]),
        .I2(rng_reg[29]),
        .I3(rng_reg[28]),
        .I4(i__carry_i_54_n_0),
        .O(i__carry_i_28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'h2BB2B22B)) 
    i__carry_i_29
       (.I0(i__carry_i_55_n_0),
        .I1(i__carry_i_56_n_0),
        .I2(rng_reg[39]),
        .I3(rng_reg[37]),
        .I4(rng_reg[38]),
        .O(i__carry_i_29_n_0));
  LUT6 #(
    .INIT(64'h6996966996696996)) 
    i__carry_i_3
       (.I0(i__carry_i_10_n_0),
        .I1(i__carry_i_11_n_0),
        .I2(i__carry_i_12_n_0),
        .I3(\num_of_1s_reg_n_0_[1] ),
        .I4(i__carry_i_13_n_0),
        .I5(i__carry_i_14_n_0),
        .O(i__carry_i_3_n_0));
  LUT6 #(
    .INIT(64'hA99595A995A9A995)) 
    i__carry_i_30
       (.I0(i__carry_i_57_n_0),
        .I1(rng_reg[0]),
        .I2(i__carry_i_44_n_0),
        .I3(rng_reg[59]),
        .I4(rng_reg[58]),
        .I5(rng_reg[60]),
        .O(i__carry_i_30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_31
       (.I0(i__carry_i_58_n_0),
        .I1(i__carry_i_59_n_0),
        .I2(i__carry_i_60_n_0),
        .O(i__carry_i_31_n_0));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT5 #(
    .INIT(32'hE81717E8)) 
    i__carry_i_32
       (.I0(rng_reg[44]),
        .I1(rng_reg[43]),
        .I2(rng_reg[45]),
        .I3(i__carry_i_61_n_0),
        .I4(i__carry_i_62_n_0),
        .O(i__carry_i_32_n_0));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT5 #(
    .INIT(32'h99969666)) 
    i__carry_i_33
       (.I0(i__carry_i_63_n_0),
        .I1(i__carry_i_64_n_0),
        .I2(rng_reg[54]),
        .I3(rng_reg[53]),
        .I4(rng_reg[52]),
        .O(i__carry_i_33_n_0));
  LUT4 #(
    .INIT(16'h17E8)) 
    i__carry_i_34
       (.I0(rng_reg[34]),
        .I1(rng_reg[35]),
        .I2(rng_reg[36]),
        .I3(i__carry_i_65_n_0),
        .O(i__carry_i_34_n_0));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_35
       (.I0(i__carry_i_50_n_0),
        .I1(i__carry_i_49_n_0),
        .I2(i__carry_i_48_n_0),
        .O(i__carry_i_35_n_0));
  LUT6 #(
    .INIT(64'hFFFF966996690000)) 
    i__carry_i_36
       (.I0(i__carry_i_39_n_0),
        .I1(rng_reg[28]),
        .I2(rng_reg[29]),
        .I3(rng_reg[30]),
        .I4(i__carry_i_41_n_0),
        .I5(i__carry_i_40_n_0),
        .O(i__carry_i_36_n_0));
  LUT4 #(
    .INIT(16'h6996)) 
    i__carry_i_37
       (.I0(rng_reg[20]),
        .I1(rng_reg[19]),
        .I2(rng_reg[21]),
        .I3(i__carry_i_66_n_0),
        .O(i__carry_i_37_n_0));
  LUT4 #(
    .INIT(16'h9669)) 
    i__carry_i_38
       (.I0(rng_reg[7]),
        .I1(rng_reg[8]),
        .I2(rng_reg[9]),
        .I3(i__carry_i_67_n_0),
        .O(i__carry_i_38_n_0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    i__carry_i_39
       (.I0(rng_reg[25]),
        .I1(rng_reg[26]),
        .I2(rng_reg[27]),
        .I3(rng_reg[22]),
        .I4(rng_reg[23]),
        .I5(rng_reg[24]),
        .O(i__carry_i_39_n_0));
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_4
       (.I0(i__carry_i_15_n_0),
        .I1(i__carry_i_16_n_0),
        .I2(i__carry_i_17_n_0),
        .I3(\num_of_1s_reg_n_0_[0] ),
        .I4(i__carry_i_18_n_0),
        .O(i__carry_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT5 #(
    .INIT(32'h69969669)) 
    i__carry_i_40
       (.I0(i__carry_i_55_n_0),
        .I1(i__carry_i_56_n_0),
        .I2(rng_reg[38]),
        .I3(rng_reg[37]),
        .I4(rng_reg[39]),
        .O(i__carry_i_40_n_0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    i__carry_i_41
       (.I0(i__carry_i_51_n_0),
        .I1(i__carry_i_52_n_0),
        .I2(rng_reg[44]),
        .I3(rng_reg[43]),
        .I4(rng_reg[45]),
        .O(i__carry_i_41_n_0));
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_42
       (.I0(rng_reg[57]),
        .I1(rng_reg[55]),
        .I2(rng_reg[56]),
        .O(i__carry_i_42_n_0));
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_43
       (.I0(rng_reg[52]),
        .I1(rng_reg[54]),
        .I2(rng_reg[53]),
        .O(i__carry_i_43_n_0));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_44
       (.I0(rng_reg[63]),
        .I1(rng_reg[61]),
        .I2(rng_reg[62]),
        .O(i__carry_i_44_n_0));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'hFF171700)) 
    i__carry_i_45
       (.I0(rng_reg[56]),
        .I1(rng_reg[55]),
        .I2(rng_reg[57]),
        .I3(i__carry_i_68_n_0),
        .I4(i__carry_i_69_n_0),
        .O(i__carry_i_45_n_0));
  LUT6 #(
    .INIT(64'h8E8E8E008E000000)) 
    i__carry_i_46
       (.I0(i__carry_i_43_n_0),
        .I1(i__carry_i_42_n_0),
        .I2(i__carry_i_70_n_0),
        .I3(rng_reg[0]),
        .I4(i__carry_i_44_n_0),
        .I5(i__carry_i_71_n_0),
        .O(i__carry_i_46_n_0));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_47
       (.I0(i__carry__0_i_19_n_0),
        .I1(i__carry__0_i_21_n_0),
        .I2(i__carry__0_i_20_n_0),
        .O(i__carry_i_47_n_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'h66696999)) 
    i__carry_i_48
       (.I0(i__carry__0_i_23_n_0),
        .I1(i__carry__0_i_22_n_0),
        .I2(rng_reg[9]),
        .I3(rng_reg[7]),
        .I4(rng_reg[8]),
        .O(i__carry_i_48_n_0));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hE81717E8)) 
    i__carry_i_49
       (.I0(rng_reg[16]),
        .I1(rng_reg[17]),
        .I2(rng_reg[18]),
        .I3(i__carry__0_i_25_n_0),
        .I4(i__carry__0_i_24_n_0),
        .O(i__carry_i_49_n_0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry_i_5
       (.I0(i__carry_i_11_n_0),
        .I1(i__carry_i_10_n_0),
        .I2(i__carry_i_12_n_0),
        .O(i__carry_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'hE81717E8)) 
    i__carry_i_50
       (.I0(rng_reg[25]),
        .I1(rng_reg[26]),
        .I2(rng_reg[27]),
        .I3(i__carry__0_i_27_n_0),
        .I4(i__carry__0_i_26_n_0),
        .O(i__carry_i_50_n_0));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'h69)) 
    i__carry_i_51
       (.I0(rng_reg[40]),
        .I1(rng_reg[41]),
        .I2(rng_reg[42]),
        .O(i__carry_i_51_n_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h69)) 
    i__carry_i_52
       (.I0(rng_reg[46]),
        .I1(rng_reg[47]),
        .I2(rng_reg[48]),
        .O(i__carry_i_52_n_0));
  LUT6 #(
    .INIT(64'h69FFFF69FF6969FF)) 
    i__carry_i_53
       (.I0(rng_reg[24]),
        .I1(rng_reg[23]),
        .I2(rng_reg[22]),
        .I3(rng_reg[27]),
        .I4(rng_reg[26]),
        .I5(rng_reg[25]),
        .O(i__carry_i_53_n_0));
  LUT6 #(
    .INIT(64'hFF9696FF96FFFF96)) 
    i__carry_i_54
       (.I0(rng_reg[24]),
        .I1(rng_reg[23]),
        .I2(rng_reg[22]),
        .I3(rng_reg[27]),
        .I4(rng_reg[26]),
        .I5(rng_reg[25]),
        .O(i__carry_i_54_n_0));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'h69)) 
    i__carry_i_55
       (.I0(rng_reg[34]),
        .I1(rng_reg[35]),
        .I2(rng_reg[36]),
        .O(i__carry_i_55_n_0));
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_56
       (.I0(rng_reg[31]),
        .I1(rng_reg[32]),
        .I2(rng_reg[33]),
        .O(i__carry_i_56_n_0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT5 #(
    .INIT(32'hFF969600)) 
    i__carry_i_57
       (.I0(rng_reg[49]),
        .I1(rng_reg[51]),
        .I2(rng_reg[50]),
        .I3(i__carry_i_42_n_0),
        .I4(i__carry_i_43_n_0),
        .O(i__carry_i_57_n_0));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT5 #(
    .INIT(32'h66696999)) 
    i__carry_i_58
       (.I0(i__carry_i_69_n_0),
        .I1(i__carry_i_68_n_0),
        .I2(rng_reg[57]),
        .I3(rng_reg[55]),
        .I4(rng_reg[56]),
        .O(i__carry_i_58_n_0));
  LUT5 #(
    .INIT(32'h2882AAAA)) 
    i__carry_i_59
       (.I0(i__carry_i_72_n_0),
        .I1(rng_reg[9]),
        .I2(rng_reg[8]),
        .I3(rng_reg[7]),
        .I4(i__carry_i_73_n_0),
        .O(i__carry_i_59_n_0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'h2BB2B22B)) 
    i__carry_i_6
       (.I0(i__carry_i_14_n_0),
        .I1(i__carry_i_13_n_0),
        .I2(i__carry_i_10_n_0),
        .I3(i__carry_i_11_n_0),
        .I4(i__carry_i_12_n_0),
        .O(i__carry_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'h6900FFFF)) 
    i__carry_i_60
       (.I0(rng_reg[21]),
        .I1(rng_reg[19]),
        .I2(rng_reg[20]),
        .I3(i__carry_i_74_n_0),
        .I4(i__carry_i_75_n_0),
        .O(i__carry_i_60_n_0));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry_i_61
       (.I0(rng_reg[42]),
        .I1(rng_reg[41]),
        .I2(rng_reg[40]),
        .O(i__carry_i_61_n_0));
  LUT3 #(
    .INIT(8'h17)) 
    i__carry_i_62
       (.I0(rng_reg[38]),
        .I1(rng_reg[37]),
        .I2(rng_reg[39]),
        .O(i__carry_i_62_n_0));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry_i_63
       (.I0(rng_reg[50]),
        .I1(rng_reg[51]),
        .I2(rng_reg[49]),
        .O(i__carry_i_63_n_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    i__carry_i_64
       (.I0(rng_reg[48]),
        .I1(rng_reg[47]),
        .I2(rng_reg[46]),
        .O(i__carry_i_64_n_0));
  LUT6 #(
    .INIT(64'h171717E817E8E8E8)) 
    i__carry_i_65
       (.I0(rng_reg[33]),
        .I1(rng_reg[32]),
        .I2(rng_reg[31]),
        .I3(rng_reg[29]),
        .I4(rng_reg[28]),
        .I5(rng_reg[30]),
        .O(i__carry_i_65_n_0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    i__carry_i_66
       (.I0(rng_reg[16]),
        .I1(rng_reg[17]),
        .I2(rng_reg[18]),
        .I3(rng_reg[13]),
        .I4(rng_reg[14]),
        .I5(rng_reg[15]),
        .O(i__carry_i_66_n_0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    i__carry_i_67
       (.I0(rng_reg[4]),
        .I1(rng_reg[5]),
        .I2(rng_reg[6]),
        .I3(rng_reg[10]),
        .I4(rng_reg[11]),
        .I5(rng_reg[12]),
        .O(i__carry_i_67_n_0));
  LUT3 #(
    .INIT(8'h17)) 
    i__carry_i_68
       (.I0(rng_reg[60]),
        .I1(rng_reg[58]),
        .I2(rng_reg[59]),
        .O(i__carry_i_68_n_0));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'h17)) 
    i__carry_i_69
       (.I0(rng_reg[63]),
        .I1(rng_reg[61]),
        .I2(rng_reg[62]),
        .O(i__carry_i_69_n_0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h9669)) 
    i__carry_i_7
       (.I0(i__carry_i_19_n_0),
        .I1(i__carry_i_20_n_0),
        .I2(i__carry_i_21_n_0),
        .I3(i__carry_i_22_n_0),
        .O(i__carry_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'h69)) 
    i__carry_i_70
       (.I0(rng_reg[49]),
        .I1(rng_reg[51]),
        .I2(rng_reg[50]),
        .O(i__carry_i_70_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h96)) 
    i__carry_i_71
       (.I0(rng_reg[60]),
        .I1(rng_reg[58]),
        .I2(rng_reg[59]),
        .O(i__carry_i_71_n_0));
  LUT6 #(
    .INIT(64'h69FFFF69FF6969FF)) 
    i__carry_i_72
       (.I0(rng_reg[12]),
        .I1(rng_reg[11]),
        .I2(rng_reg[10]),
        .I3(rng_reg[6]),
        .I4(rng_reg[5]),
        .I5(rng_reg[4]),
        .O(i__carry_i_72_n_0));
  LUT6 #(
    .INIT(64'hFF9696FF96FFFF96)) 
    i__carry_i_73
       (.I0(rng_reg[12]),
        .I1(rng_reg[11]),
        .I2(rng_reg[10]),
        .I3(rng_reg[6]),
        .I4(rng_reg[5]),
        .I5(rng_reg[4]),
        .O(i__carry_i_73_n_0));
  LUT6 #(
    .INIT(64'h69FFFF69FF6969FF)) 
    i__carry_i_74
       (.I0(rng_reg[15]),
        .I1(rng_reg[14]),
        .I2(rng_reg[13]),
        .I3(rng_reg[18]),
        .I4(rng_reg[17]),
        .I5(rng_reg[16]),
        .O(i__carry_i_74_n_0));
  LUT6 #(
    .INIT(64'hFF9696FF96FFFF96)) 
    i__carry_i_75
       (.I0(rng_reg[15]),
        .I1(rng_reg[14]),
        .I2(rng_reg[13]),
        .I3(rng_reg[18]),
        .I4(rng_reg[17]),
        .I5(rng_reg[16]),
        .O(i__carry_i_75_n_0));
  LUT6 #(
    .INIT(64'h87E11E871E87781E)) 
    i__carry_i_8
       (.I0(i__carry_i_21_n_0),
        .I1(i__carry_i_22_n_0),
        .I2(i__carry_i_23_n_0),
        .I3(i__carry_i_24_n_0),
        .I4(i__carry_i_25_n_0),
        .I5(i__carry_i_26_n_0),
        .O(i__carry_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT4 #(
    .INIT(16'h0096)) 
    i__carry_i_9
       (.I0(i__carry_i_22_n_0),
        .I1(i__carry_i_21_n_0),
        .I2(i__carry_i_20_n_0),
        .I3(i__carry_i_19_n_0),
        .O(i__carry_i_9_n_0));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \num_of_1s0_inferred__0/i__carry 
       (.CI(1'b0),
        .CO({\num_of_1s0_inferred__0/i__carry_n_0 ,\num_of_1s0_inferred__0/i__carry_n_1 ,\num_of_1s0_inferred__0/i__carry_n_2 ,\num_of_1s0_inferred__0/i__carry_n_3 }),
        .CYINIT(1'b0),
        .DI({\num_of_1s_reg_n_0_[3] ,\num_of_1s_reg_n_0_[2] ,\num_of_1s_reg_n_0_[1] ,\num_of_1s_reg_n_0_[0] }),
        .O(p_0_in[3:0]),
        .S({i__carry_i_1_n_0,i__carry_i_2_n_0,i__carry_i_3_n_0,i__carry_i_4_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \num_of_1s0_inferred__0/i__carry__0 
       (.CI(\num_of_1s0_inferred__0/i__carry_n_0 ),
        .CO({\num_of_1s0_inferred__0/i__carry__0_n_0 ,\num_of_1s0_inferred__0/i__carry__0_n_1 ,\num_of_1s0_inferred__0/i__carry__0_n_2 ,\num_of_1s0_inferred__0/i__carry__0_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,\num_of_1s_reg_n_0_[6] ,\num_of_1s_reg_n_0_[5] ,\num_of_1s_reg_n_0_[4] }),
        .O(p_0_in[7:4]),
        .S({\num_of_1s_reg_n_0_[7] ,i__carry__0_i_1_n_0,i__carry__0_i_2_n_0,i__carry__0_i_3_n_0}));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \num_of_1s0_inferred__0/i__carry__1 
       (.CI(\num_of_1s0_inferred__0/i__carry__0_n_0 ),
        .CO({\num_of_1s0_inferred__0/i__carry__1_n_0 ,\num_of_1s0_inferred__0/i__carry__1_n_1 ,\num_of_1s0_inferred__0/i__carry__1_n_2 ,\num_of_1s0_inferred__0/i__carry__1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(p_0_in[11:8]),
        .S({\num_of_1s_reg_n_0_[11] ,\num_of_1s_reg_n_0_[10] ,\num_of_1s_reg_n_0_[9] ,\num_of_1s_reg_n_0_[8] }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \num_of_1s0_inferred__0/i__carry__2 
       (.CI(\num_of_1s0_inferred__0/i__carry__1_n_0 ),
        .CO({\num_of_1s0_inferred__0/i__carry__2_n_0 ,\num_of_1s0_inferred__0/i__carry__2_n_1 ,\num_of_1s0_inferred__0/i__carry__2_n_2 ,\num_of_1s0_inferred__0/i__carry__2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(p_0_in[15:12]),
        .S({\num_of_1s_reg_n_0_[15] ,\num_of_1s_reg_n_0_[14] ,\num_of_1s_reg_n_0_[13] ,\num_of_1s_reg_n_0_[12] }));
  (* ADDER_THRESHOLD = "35" *) 
  CARRY4 \num_of_1s0_inferred__0/i__carry__3 
       (.CI(\num_of_1s0_inferred__0/i__carry__2_n_0 ),
        .CO({\NLW_num_of_1s0_inferred__0/i__carry__3_CO_UNCONNECTED [3],\num_of_1s0_inferred__0/i__carry__3_n_1 ,\num_of_1s0_inferred__0/i__carry__3_n_2 ,\num_of_1s0_inferred__0/i__carry__3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(p_0_in[19:16]),
        .S({\num_of_1s_reg_n_0_[19] ,\num_of_1s_reg_n_0_[18] ,\num_of_1s_reg_n_0_[17] ,\num_of_1s_reg_n_0_[16] }));
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    \num_of_1s[19]_i_1 
       (.I0(Q[0]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[4]),
        .I4(Q[3]),
        .O(stat_trng_rst));
  LUT2 #(
    .INIT(4'h2)) 
    \num_of_1s[19]_i_2 
       (.I0(rng_ready_d0),
        .I1(rng_ready_d1),
        .O(E));
  FDRE \num_of_1s_reg[0] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\num_of_1s_reg_n_0_[0] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[10] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[10]),
        .Q(\num_of_1s_reg_n_0_[10] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[11] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[11]),
        .Q(\num_of_1s_reg_n_0_[11] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[12] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[12]),
        .Q(\num_of_1s_reg_n_0_[12] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[13] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[13]),
        .Q(\num_of_1s_reg_n_0_[13] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[14] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[14]),
        .Q(\num_of_1s_reg_n_0_[14] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[15] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[15]),
        .Q(\num_of_1s_reg_n_0_[15] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[16] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[16]),
        .Q(\num_of_1s_reg_n_0_[16] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[17] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[17]),
        .Q(\num_of_1s_reg_n_0_[17] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[18] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[18]),
        .Q(\num_of_1s_reg_n_0_[18] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[19] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[19]),
        .Q(\num_of_1s_reg_n_0_[19] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[1] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\num_of_1s_reg_n_0_[1] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[2] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\num_of_1s_reg_n_0_[2] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[3] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[3]),
        .Q(\num_of_1s_reg_n_0_[3] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[4] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\num_of_1s_reg_n_0_[4] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[5] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[5]),
        .Q(\num_of_1s_reg_n_0_[5] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[6] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[6]),
        .Q(\num_of_1s_reg_n_0_[6] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[7] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[7]),
        .Q(\num_of_1s_reg_n_0_[7] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[8] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[8]),
        .Q(\num_of_1s_reg_n_0_[8] ),
        .R(stat_trng_rst));
  FDRE \num_of_1s_reg[9] 
       (.C(clk),
        .CE(E),
        .D(p_0_in[9]),
        .Q(\num_of_1s_reg_n_0_[9] ),
        .R(stat_trng_rst));
  FDRE rng_ready_d0_reg
       (.C(clk),
        .CE(1'b1),
        .D(rng_ready),
        .Q(rng_ready_d0),
        .R(1'b0));
  FDRE rng_ready_d1_reg
       (.C(clk),
        .CE(1'b1),
        .D(rng_ready_d0),
        .Q(rng_ready_d1),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    \rng_word_counter[0]_i_1 
       (.I0(rng_ready_d1),
        .I1(rng_ready_d0),
        .I2(stat_done),
        .O(rng_word_counter0));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \rng_word_counter[0]_i_3 
       (.I0(\rng_word_counter[0]_i_5_n_0 ),
        .I1(rng_word_counter_reg[15]),
        .I2(rng_word_counter_reg[19]),
        .I3(rng_word_counter_reg[10]),
        .I4(rng_word_counter_reg[1]),
        .I5(\rng_word_counter[0]_i_6_n_0 ),
        .O(stat_done));
  LUT1 #(
    .INIT(2'h1)) 
    \rng_word_counter[0]_i_4 
       (.I0(rng_word_counter_reg[0]),
        .O(\rng_word_counter[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \rng_word_counter[0]_i_5 
       (.I0(rng_word_counter_reg[11]),
        .I1(rng_word_counter_reg[17]),
        .I2(rng_word_counter_reg[0]),
        .I3(rng_word_counter_reg[6]),
        .O(\rng_word_counter[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \rng_word_counter[0]_i_6 
       (.I0(rng_word_counter_reg[7]),
        .I1(rng_word_counter_reg[16]),
        .I2(rng_word_counter_reg[2]),
        .I3(rng_word_counter_reg[5]),
        .I4(\rng_word_counter[0]_i_7_n_0 ),
        .I5(\rng_word_counter[0]_i_8_n_0 ),
        .O(\rng_word_counter[0]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hFFDF)) 
    \rng_word_counter[0]_i_7 
       (.I0(rng_word_counter_reg[13]),
        .I1(rng_word_counter_reg[18]),
        .I2(rng_word_counter_reg[3]),
        .I3(rng_word_counter_reg[14]),
        .O(\rng_word_counter[0]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \rng_word_counter[0]_i_8 
       (.I0(rng_word_counter_reg[12]),
        .I1(rng_word_counter_reg[8]),
        .I2(rng_word_counter_reg[9]),
        .I3(rng_word_counter_reg[4]),
        .O(\rng_word_counter[0]_i_8_n_0 ));
  FDRE \rng_word_counter_reg[0] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[0]_i_2_n_7 ),
        .Q(rng_word_counter_reg[0]),
        .R(stat_trng_rst));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \rng_word_counter_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\rng_word_counter_reg[0]_i_2_n_0 ,\rng_word_counter_reg[0]_i_2_n_1 ,\rng_word_counter_reg[0]_i_2_n_2 ,\rng_word_counter_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\rng_word_counter_reg[0]_i_2_n_4 ,\rng_word_counter_reg[0]_i_2_n_5 ,\rng_word_counter_reg[0]_i_2_n_6 ,\rng_word_counter_reg[0]_i_2_n_7 }),
        .S({rng_word_counter_reg[3:1],\rng_word_counter[0]_i_4_n_0 }));
  FDRE \rng_word_counter_reg[10] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[8]_i_1_n_5 ),
        .Q(rng_word_counter_reg[10]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[11] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[8]_i_1_n_4 ),
        .Q(rng_word_counter_reg[11]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[12] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[12]_i_1_n_7 ),
        .Q(rng_word_counter_reg[12]),
        .R(stat_trng_rst));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \rng_word_counter_reg[12]_i_1 
       (.CI(\rng_word_counter_reg[8]_i_1_n_0 ),
        .CO({\rng_word_counter_reg[12]_i_1_n_0 ,\rng_word_counter_reg[12]_i_1_n_1 ,\rng_word_counter_reg[12]_i_1_n_2 ,\rng_word_counter_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rng_word_counter_reg[12]_i_1_n_4 ,\rng_word_counter_reg[12]_i_1_n_5 ,\rng_word_counter_reg[12]_i_1_n_6 ,\rng_word_counter_reg[12]_i_1_n_7 }),
        .S(rng_word_counter_reg[15:12]));
  FDRE \rng_word_counter_reg[13] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[12]_i_1_n_6 ),
        .Q(rng_word_counter_reg[13]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[14] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[12]_i_1_n_5 ),
        .Q(rng_word_counter_reg[14]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[15] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[12]_i_1_n_4 ),
        .Q(rng_word_counter_reg[15]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[16] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[16]_i_1_n_7 ),
        .Q(rng_word_counter_reg[16]),
        .R(stat_trng_rst));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \rng_word_counter_reg[16]_i_1 
       (.CI(\rng_word_counter_reg[12]_i_1_n_0 ),
        .CO({\NLW_rng_word_counter_reg[16]_i_1_CO_UNCONNECTED [3],\rng_word_counter_reg[16]_i_1_n_1 ,\rng_word_counter_reg[16]_i_1_n_2 ,\rng_word_counter_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rng_word_counter_reg[16]_i_1_n_4 ,\rng_word_counter_reg[16]_i_1_n_5 ,\rng_word_counter_reg[16]_i_1_n_6 ,\rng_word_counter_reg[16]_i_1_n_7 }),
        .S(rng_word_counter_reg[19:16]));
  FDRE \rng_word_counter_reg[17] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[16]_i_1_n_6 ),
        .Q(rng_word_counter_reg[17]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[18] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[16]_i_1_n_5 ),
        .Q(rng_word_counter_reg[18]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[19] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[16]_i_1_n_4 ),
        .Q(rng_word_counter_reg[19]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[1] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[0]_i_2_n_6 ),
        .Q(rng_word_counter_reg[1]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[2] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[0]_i_2_n_5 ),
        .Q(rng_word_counter_reg[2]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[3] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[0]_i_2_n_4 ),
        .Q(rng_word_counter_reg[3]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[4] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[4]_i_1_n_7 ),
        .Q(rng_word_counter_reg[4]),
        .R(stat_trng_rst));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \rng_word_counter_reg[4]_i_1 
       (.CI(\rng_word_counter_reg[0]_i_2_n_0 ),
        .CO({\rng_word_counter_reg[4]_i_1_n_0 ,\rng_word_counter_reg[4]_i_1_n_1 ,\rng_word_counter_reg[4]_i_1_n_2 ,\rng_word_counter_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rng_word_counter_reg[4]_i_1_n_4 ,\rng_word_counter_reg[4]_i_1_n_5 ,\rng_word_counter_reg[4]_i_1_n_6 ,\rng_word_counter_reg[4]_i_1_n_7 }),
        .S(rng_word_counter_reg[7:4]));
  FDRE \rng_word_counter_reg[5] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[4]_i_1_n_6 ),
        .Q(rng_word_counter_reg[5]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[6] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[4]_i_1_n_5 ),
        .Q(rng_word_counter_reg[6]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[7] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[4]_i_1_n_4 ),
        .Q(rng_word_counter_reg[7]),
        .R(stat_trng_rst));
  FDRE \rng_word_counter_reg[8] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[8]_i_1_n_7 ),
        .Q(rng_word_counter_reg[8]),
        .R(stat_trng_rst));
  (* ADDER_THRESHOLD = "11" *) 
  CARRY4 \rng_word_counter_reg[8]_i_1 
       (.CI(\rng_word_counter_reg[4]_i_1_n_0 ),
        .CO({\rng_word_counter_reg[8]_i_1_n_0 ,\rng_word_counter_reg[8]_i_1_n_1 ,\rng_word_counter_reg[8]_i_1_n_2 ,\rng_word_counter_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\rng_word_counter_reg[8]_i_1_n_4 ,\rng_word_counter_reg[8]_i_1_n_5 ,\rng_word_counter_reg[8]_i_1_n_6 ,\rng_word_counter_reg[8]_i_1_n_7 }),
        .S(rng_word_counter_reg[11:8]));
  FDRE \rng_word_counter_reg[9] 
       (.C(clk),
        .CE(rng_word_counter0),
        .D(\rng_word_counter_reg[8]_i_1_n_6 ),
        .Q(rng_word_counter_reg[9]),
        .R(stat_trng_rst));
  LUT5 #(
    .INIT(32'hFFAACFAA)) 
    stat_error_i_1
       (.I0(stat_error),
        .I1(stat_error_i_2_n_0),
        .I2(stat_error_i_3_n_0),
        .I3(stat_done),
        .I4(stat_error_i_4_n_0),
        .O(stat_error_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAA8AAAAA8A8A8A8)) 
    stat_error_i_2
       (.I0(\num_of_1s_reg_n_0_[13] ),
        .I1(\num_of_1s_reg_n_0_[11] ),
        .I2(\num_of_1s_reg_n_0_[12] ),
        .I3(stat_error_i_5_n_0),
        .I4(stat_error_i_6_n_0),
        .I5(\num_of_1s_reg_n_0_[10] ),
        .O(stat_error_i_2_n_0));
  LUT6 #(
    .INIT(64'hBAAAAAAAAAAAAAAA)) 
    stat_error_i_3
       (.I0(\num_of_1s_reg_n_0_[13] ),
        .I1(stat_error_i_6_n_0),
        .I2(\num_of_1s_reg_n_0_[11] ),
        .I3(\num_of_1s_reg_n_0_[10] ),
        .I4(\num_of_1s_reg_n_0_[12] ),
        .I5(stat_error_i_7_n_0),
        .O(stat_error_i_3_n_0));
  LUT6 #(
    .INIT(64'hFDFFFFFFFFFFFFFF)) 
    stat_error_i_4
       (.I0(\num_of_1s_reg_n_0_[18] ),
        .I1(\num_of_1s_reg_n_0_[14] ),
        .I2(\num_of_1s_reg_n_0_[19] ),
        .I3(\num_of_1s_reg_n_0_[16] ),
        .I4(\num_of_1s_reg_n_0_[15] ),
        .I5(\num_of_1s_reg_n_0_[17] ),
        .O(stat_error_i_4_n_0));
  LUT3 #(
    .INIT(8'hA8)) 
    stat_error_i_5
       (.I0(\num_of_1s_reg_n_0_[8] ),
        .I1(\num_of_1s_reg_n_0_[5] ),
        .I2(\num_of_1s_reg_n_0_[3] ),
        .O(stat_error_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h11111113)) 
    stat_error_i_6
       (.I0(\num_of_1s_reg_n_0_[8] ),
        .I1(\num_of_1s_reg_n_0_[9] ),
        .I2(\num_of_1s_reg_n_0_[7] ),
        .I3(\num_of_1s_reg_n_0_[6] ),
        .I4(\num_of_1s_reg_n_0_[4] ),
        .O(stat_error_i_6_n_0));
  LUT6 #(
    .INIT(64'hEAEAEAEAEAEAEAAA)) 
    stat_error_i_7
       (.I0(stat_error_i_8_n_0),
        .I1(\num_of_1s_reg_n_0_[3] ),
        .I2(\num_of_1s_reg_n_0_[5] ),
        .I3(\num_of_1s_reg_n_0_[1] ),
        .I4(\num_of_1s_reg_n_0_[0] ),
        .I5(\num_of_1s_reg_n_0_[2] ),
        .O(stat_error_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    stat_error_i_8
       (.I0(\num_of_1s_reg_n_0_[9] ),
        .I1(\num_of_1s_reg_n_0_[7] ),
        .I2(\num_of_1s_reg_n_0_[6] ),
        .O(stat_error_i_8_n_0));
  FDRE stat_error_reg
       (.C(clk),
        .CE(1'b1),
        .D(stat_error_i_1_n_0),
        .Q(stat_error),
        .R(1'b0));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
QGLtnqZzRetDH6gCWT4Js6wuLlZfrNx/VJp3sfR2NF+cxypO5AxN0oDKLJJtmdrtE/ueNDg+Qf7Z
TqBNRojORA==

`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
B6Ger3hRvfjHkaJ+W8639Kl3TzC9TogLuklOXEiMNdc4Im+DjEUzxb3DKlzu0VW3zxZqjJ3+wsW/
LnRmPCESi5Y9eRJaLFXg79EMfoj4X+nTdHAP6yCfltBADKegZ12gpnB/8ey5yn2KA74LUtPC7jna
iyjqSfsWLGnz6UdXzwk=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
BX+DxgMPRyZbYojCUR9Sk8Lq+3ZigBz4yMFHQkmurfdfDzyTPJCE827eGiPyTenK1QPVhEtf9g06
0BFXq/0COPuU1BWJwdkz1c4dE6/exDwhvEh+hPx3vRY6z8fDEf6aGVIXrHDvrmddehe7yMSIpo+k
aXHR06EEdfHCFY4TggYwhcJVXjkE+ApsVuyfmEfPmYjo8hCWyQyBsUWIOY03q1+MvUjjsmTwgs9g
fh5MY9ToaLfoJxPKdCpsqrBX4LJ+VDGFlAqIcqHTE2jCmPiToZAFXB7fzf1wDjFCBlJyFVDBGi0i
m+CouLSb7X1mvVhdDZgNrZDJMV688Bu3o54vew==

`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
DaIU/Ddc8USbZ2mURzujJDWDH1JbHl5tFVOOQ2aVaUPIA71yyE38OXVLEtF8rNmujYH30nEeQ+FV
LVJ16aaHw+iiuaqorTM3K5KLohVlN+WlcEtSXHuPNHjw8ddqtzpaX7pH1zqZH+YmfCL5oaNLqDH4
rkBnUl0/Gm/hzSwKjYhXGQFYQ+gGP99OjXakzrAqZzp/Iq4gt+Z5902/JV9thd/isHQImJ0QyK8M
EKM579iPAfXGes2mbiNYHcvDmSPYmW1zlhOE++N1EKeea7j/msnKeyhlC+hGE4Xfn4TVvqgQexCT
rp/wS/MosY6WH1aKFQlFH2hEppA7KXUaQlvG+w==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
XmWoAt4X8hrCJ5yTyug4ajJW5UhfkLNibzjihWzZ4Cr9hQSvWZoTc8rjGsLPbz6Le+/9iI5KxecS
eR0wiAO+G2IkwhZgVBeZdKoFnlnTVAyLjk9wMAFXNyJZM6b1NDbfXlPcUsC6JePvPlwwdWknkSsC
r3KvgkWAS+O3xvRmaNw=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
Hw3Y+rShKrXiUViyNU1/O2qv6TgheLHBnFMj1i9MUGrHYqh9pLfLYUgWR7S2vj4jv4S+Ks0BpP4p
dKEqVAFmTCfQNEUHaVcFPkOHgig6L4mhLY6HUUKJoRgiQepgLi/W3V+ZZPQSQFkB3CU4MsJzhXvR
yLcpDriZy8cnAHD87Zi5DrNGBzj3kigJeM0du6lCQbxtF5aEdoaNP+YTnIFtcqYhoYnswQlYt0sV
HKgFA8VzqzL5WYnpH7+1IKmFkJBHkyqHCa9wPK0qCKnxkuDj70YzPVqQ+cocdKU+/gNdpCOdZlci
F2HTxrgfrXndJru3TiDqu4UavqAe0MNuFp3t0w==

`pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
XPVggoWL6aXz+MpODTOZhEUQDa0vfEnUDaYeEHXm2vGyqKJujN2c/FFAFBeBYdJATLsIsQ+BqoPc
pBbcFYXDBfOtFIW2dH6Y1OoD65KyJ/hAq8coa21kFgq4hFat5vzZ2iIfkCpTUr4vDZO7Xne8cZO9
WsHffoTCt5rS59wWm2b8I5R8Eh2TUbQg3RCyrcnD66cvcEnlXe1CNMQ4/loVJpA4IBinBf820Wjc
vw2fZbGI0jXC+ACSHOviH63Xwmn+aRV5Ppkup7IYoon/ieKapRQeASu3TTY37xSBXiInSdtMTzJ6
+4GfO4eSHVriCk/sWbuTBzfRzoSShrnHjzz5LA==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
L78XuiswVcgO2gtebzL7SA9BC/jJGAM0v6S9pzmyqL+QYzRneiYeGyDmsW33jEVVSTuNjTXkBLY7
yTOKQruatwe4V0OLi6174saSAmPgerSV1GyLP7KhmusLV/N61avC9TPam+tekhKeE0tds4EnJ3et
4JdLh+SE4Z4pcuqCjB5MFneIYKKWDx7siU6oesAQtoSJOesfMchX63MhOjOHFP/ch+1gHv3T45hg
IGF7V7TrdREVE4f9631tlVJ1o2Dypsmo/76Itz5WCGlTMjAnWXN8IXxKN+PZ3dyt1wjrZm2P/td+
xiGszFnSLrRvw/HferwtSmRx8q0fiHZ88roGTw==

`pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
kDX5kq2QEe25429T6vQqBCFvV1McKTJRYfK99ymVNK2GGvGLXSzgwJHwB2fj9rM0wme3zYYY0vQR
x+9F4L7KLlOVY6qY3LB59uDzyXBI3mMZaS905HXHJkdZHWtQWpfHhl27LqL+8FSluaD6F+KFfYOV
CwIOVuCIp/XjxFXpNBik7YiPt4kHOlDA97IXNLnYUn/g1csGqeNWce4UTne50ggWvLYGbTFGmTjT
N67TpUiGRVRCSv8Tax72GWFIMFZk3Tlp68ZUSQEybZMWX1U9XdMdtxfvNGhf8mi5jQJ2SupSzKu4
T/+53IN9T8aLePAiGBKKG1ZBj4y1ZyYA7XYvjw==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 48400)
`pragma protect data_block
MSPqm5YKPtDOV1azYXG4AMlgFq/jmrlfd7FfiVn3Ixqt/8ChCJctQWKfNjk2J3/cMZhsgqZBQJ8c
HGD25qe8FvxSbn11PHjx510pAICmd15HJ7v1u/GIlZA2dV/bvSShzfHwcTEBX/nWlY9TCQKSrz1Y
KB6IIyXK1n98Rqf2HtEak35zseACHwbidPfSh6y0ndGggeNC9yB7j+KKDuTxAK+8ukTgepeo0HDo
lzZD40b6rQB6rmASqNfXyMexYJZuALxg23uS223wKF0u9uYFyo0sWkUgYfFSF2YUzEUtMTNIk8EJ
Z4jbawmsp/jD/6mcqGNA+z+Sh0eUGauTFbZmDutGwBXTYia31TZBGvmZHx+gwkYgeI7swi3UXGnP
tGje/t7PgQopLfCTzjJKUwT3TuGR4DITWB0cn9QxQSoMlx1v1D1hDt0E8+wSi53Hal5iD4/GuQEY
UCI8wXruSboUJINyZoPhrECV/pZi5FBWNlqEcFoAI32exV4GcRF0wvlrqJ9sLsU60Xe6lFyMRZrF
Y5N6c4v60jhp3shtWC5YU0/Rhb2eoPedQLjV+4O/r98GR7BkNNESel4eglkV4lNbGGdruvrnAGJp
UU0FcwOh3YBlTavMI6o2JL3pTD6OUwC0MZvNjGaob7eV2fy40J3wPLjgGger7R5KnZGLPqf0FJC+
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xWu7967fCQ==
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
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zHB5+a9AOw==

`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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a5HhHw6Xh2bef5pyVpw=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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onLX/ovKi1vmSTrXoYGiH93PU127c8zS/YIuhw==

`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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A26K0bI4rJ/VHL5cpusuetQlfQQrfNPL+85zGQtFZbIqlPDBG9PvZcgfGkQexKIi1ZIzqEd7J9ae
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hpmW54ZRIVFUIUo/Iaf7rXAkjybd2xt1Hbibkg==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2019_02", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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KhOJ0C+M+z5+Zbw24Vzd/m3p7iiVTp+acnwwxQ==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
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IlmkwmbTXf2+U151n8NYIhEHoNtbA91rvoWEQ/jPb7rY+1uF9dkLLzaJAr60PuQXXSTBvjnmCV/1
39OIjjSZO6cVv7bDxLA=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
AwuPeyMqg/J6Z+iq2u6vpWGK9asqvIBRvw+7fjvyFL64PnhUKzAaSeWYgULuDTuG1QCJwC8+1tM6
vE1UlEAL6iE4hEdSDoDOn6/s2zKYeNu3st3cKLxbB5YZtbXLMTA128F13D5a6y//ApmTjddUjem0
09ihCTQt0jfeDKjmR+m2wMbQrTW/uX4s1hUWCLZ6DIUl6HqUGKJ0Zx/SafYizGEZhm7+AMKrMNLr
ch37HgKjex/XwrEX7qBDlbA5HULUvY1qU7382PUKrvMaRWGodtSD0H+Gtv4pUSI2rlE8IF5i3CiU
H8r7QIWCO1PF40B8fBNDHBgkmitB9zMLWMfWmg==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26480)
`pragma protect data_block
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;
    parameter GRES_WIDTH = 10000;
    parameter GRES_START = 10000;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    wire GRESTORE;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;
    reg GRESTORE_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;
    assign (strong1, weak0) GRESTORE = GRESTORE_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

    initial begin 
	GRESTORE_int = 1'b0;
	#(GRES_START);
	GRESTORE_int = 1'b1;
	#(GRES_WIDTH);
	GRESTORE_int = 1'b0;
    end

endmodule
`endif
